nixge.txt 2.5 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192
  1. * NI XGE Ethernet controller
  2. Required properties:
  3. - compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
  4. older device trees with DMA engines co-located in the address map,
  5. with the one reg entry to describe the whole device.
  6. - reg: Address and length of the register set for the device. It contains the
  7. information of registers in the same order as described by reg-names.
  8. - reg-names: Should contain the reg names
  9. "dma": DMA engine control and status region
  10. "ctrl": MDIO and PHY control and status region
  11. - interrupts: Should contain tx and rx interrupt
  12. - interrupt-names: Should be "rx" and "tx"
  13. - phy-mode: See ethernet.txt file in the same directory.
  14. - nvmem-cells: Phandle of nvmem cell containing the MAC address
  15. - nvmem-cell-names: Should be "address"
  16. Optional properties:
  17. - mdio subnode to indicate presence of MDIO controller
  18. - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
  19. Use instead of phy-handle.
  20. - phy-handle: See ethernet.txt file in the same directory.
  21. Examples (10G generic PHY):
  22. nixge0: ethernet@40000000 {
  23. compatible = "ni,xge-enet-3.00";
  24. reg = <0x40000000 0x4000
  25. 0x41002000 0x2000>;
  26. reg-names = "dma", "ctrl";
  27. nvmem-cells = <&eth1_addr>;
  28. nvmem-cell-names = "address";
  29. interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
  30. interrupt-names = "rx", "tx";
  31. interrupt-parent = <&intc>;
  32. phy-mode = "xgmii";
  33. phy-handle = <&ethernet_phy1>;
  34. mdio {
  35. ethernet_phy1: ethernet-phy@4 {
  36. compatible = "ethernet-phy-ieee802.3-c45";
  37. reg = <4>;
  38. };
  39. };
  40. };
  41. Examples (10G generic PHY, no MDIO):
  42. nixge0: ethernet@40000000 {
  43. compatible = "ni,xge-enet-2.00";
  44. reg = <0x40000000 0x6000>;
  45. nvmem-cells = <&eth1_addr>;
  46. nvmem-cell-names = "address";
  47. interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
  48. interrupt-names = "rx", "tx";
  49. interrupt-parent = <&intc>;
  50. phy-mode = "xgmii";
  51. phy-handle = <&ethernet_phy1>;
  52. };
  53. Examples (1G generic fixed-link + MDIO):
  54. nixge0: ethernet@40000000 {
  55. compatible = "ni,xge-enet-2.00";
  56. reg = <0x40000000 0x6000>;
  57. nvmem-cells = <&eth1_addr>;
  58. nvmem-cell-names = "address";
  59. interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
  60. interrupt-names = "rx", "tx";
  61. interrupt-parent = <&intc>;
  62. phy-mode = "xgmii";
  63. fixed-link {
  64. speed = <1000>;
  65. pause;
  66. link-gpios = <&gpio0 63 GPIO_ACTIVE_HIGH>;
  67. };
  68. mdio {
  69. ethernet_phy1: ethernet-phy@4 {
  70. compatible = "ethernet-phy-ieee802.3-c22";
  71. reg = <4>;
  72. };
  73. };
  74. };