fsl,gianfar.yaml 5.9 KB

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  1. # SPDX-License-Identifier: GPL-2.0
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/net/fsl,gianfar.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Freescale Three-Speed Ethernet Controller (TSEC), "Gianfar"
  7. maintainers:
  8. - J. Neuschäfer <j.ne@posteo.net>
  9. # This is needed to distinguish gianfar.yaml and gianfar-mdio.yaml, because
  10. # both use compatible = "gianfar" (with different device_type values)
  11. select:
  12. oneOf:
  13. - properties:
  14. compatible:
  15. contains:
  16. const: gianfar
  17. device_type:
  18. const: network
  19. required:
  20. - device_type
  21. - properties:
  22. compatible:
  23. const: fsl,etsec2
  24. required:
  25. - compatible
  26. properties:
  27. compatible:
  28. enum:
  29. - gianfar
  30. - fsl,etsec2
  31. device_type:
  32. const: network
  33. model:
  34. enum:
  35. - FEC
  36. - TSEC
  37. - eTSEC
  38. reg:
  39. maxItems: 1
  40. ranges: true
  41. "#address-cells":
  42. enum: [ 1, 2 ]
  43. "#size-cells":
  44. enum: [ 1, 2 ]
  45. cell-index:
  46. $ref: /schemas/types.yaml#/definitions/uint32
  47. interrupts:
  48. minItems: 1
  49. items:
  50. - description: Transmit interrupt or single combined interrupt
  51. - description: Receive interrupt
  52. - description: Error interrupt
  53. dma-coherent: true
  54. fsl,magic-packet:
  55. type: boolean
  56. description:
  57. If present, indicates that the hardware supports waking up via magic packet.
  58. fsl,wake-on-filer:
  59. type: boolean
  60. description:
  61. If present, indicates that the hardware supports waking up by Filer
  62. General Purpose Interrupt (FGPI) asserted on the Rx int line. This is
  63. an advanced power management capability allowing certain packet types
  64. (user) defined by filer rules to wake up the system.
  65. bd-stash:
  66. type: boolean
  67. description:
  68. If present, indicates that the hardware supports stashing buffer
  69. descriptors in the L2.
  70. rx-stash-len:
  71. $ref: /schemas/types.yaml#/definitions/uint32
  72. description:
  73. Denotes the number of bytes of a received buffer to stash in the L2.
  74. rx-stash-idx:
  75. $ref: /schemas/types.yaml#/definitions/uint32
  76. description:
  77. Denotes the index of the first byte from the received buffer to stash in
  78. the L2.
  79. fsl,num_rx_queues:
  80. $ref: /schemas/types.yaml#/definitions/uint32
  81. description: Number of receive queues
  82. const: 8
  83. fsl,num_tx_queues:
  84. $ref: /schemas/types.yaml#/definitions/uint32
  85. description: Number of transmit queues
  86. const: 8
  87. tbi-handle:
  88. $ref: /schemas/types.yaml#/definitions/phandle
  89. description: Reference (phandle) to the TBI node
  90. required:
  91. - compatible
  92. - model
  93. patternProperties:
  94. "^mdio@[0-9a-f]+$":
  95. $ref: /schemas/net/fsl,gianfar-mdio.yaml#
  96. allOf:
  97. - $ref: ethernet-controller.yaml#
  98. # eTSEC2 controller nodes have "queue group" subnodes and don't need a "reg"
  99. # property.
  100. - if:
  101. properties:
  102. compatible:
  103. contains:
  104. const: fsl,etsec2
  105. then:
  106. patternProperties:
  107. "^queue-group@[0-9a-f]+$":
  108. type: object
  109. properties:
  110. reg:
  111. maxItems: 1
  112. interrupts:
  113. items:
  114. - description: Transmit interrupt
  115. - description: Receive interrupt
  116. - description: Error interrupt
  117. required:
  118. - reg
  119. - interrupts
  120. additionalProperties: false
  121. else:
  122. required:
  123. - reg
  124. # TSEC and eTSEC devices require three interrupts
  125. - if:
  126. properties:
  127. model:
  128. contains:
  129. enum: [ TSEC, eTSEC ]
  130. then:
  131. properties:
  132. interrupts:
  133. items:
  134. - description: Transmit interrupt
  135. - description: Receive interrupt
  136. - description: Error interrupt
  137. unevaluatedProperties: false
  138. examples:
  139. - |
  140. ethernet@24000 {
  141. device_type = "network";
  142. model = "TSEC";
  143. compatible = "gianfar";
  144. reg = <0x24000 0x1000>;
  145. local-mac-address = [ 00 00 00 00 00 00 ];
  146. interrupts = <29 2>, <30 2>, <34 2>;
  147. interrupt-parent = <&mpic>;
  148. phy-handle = <&phy0>;
  149. };
  150. - |
  151. #include <dt-bindings/interrupt-controller/irq.h>
  152. ethernet@24000 {
  153. compatible = "gianfar";
  154. reg = <0x24000 0x1000>;
  155. ranges = <0x0 0x24000 0x1000>;
  156. #address-cells = <1>;
  157. #size-cells = <1>;
  158. cell-index = <0>;
  159. device_type = "network";
  160. model = "eTSEC";
  161. local-mac-address = [ 00 00 00 00 00 00 ];
  162. interrupts = <32 IRQ_TYPE_LEVEL_LOW>,
  163. <33 IRQ_TYPE_LEVEL_LOW>,
  164. <34 IRQ_TYPE_LEVEL_LOW>;
  165. interrupt-parent = <&ipic>;
  166. mdio@520 {
  167. #address-cells = <1>;
  168. #size-cells = <0>;
  169. compatible = "fsl,gianfar-mdio";
  170. reg = <0x520 0x20>;
  171. };
  172. };
  173. - |
  174. #include <dt-bindings/interrupt-controller/irq.h>
  175. #include <dt-bindings/interrupt-controller/arm-gic.h>
  176. bus {
  177. #address-cells = <2>;
  178. #size-cells = <2>;
  179. ethernet {
  180. compatible = "fsl,etsec2";
  181. ranges;
  182. device_type = "network";
  183. #address-cells = <2>;
  184. #size-cells = <2>;
  185. interrupt-parent = <&gic>;
  186. model = "eTSEC";
  187. fsl,magic-packet;
  188. dma-coherent;
  189. queue-group@2d10000 {
  190. reg = <0x0 0x2d10000 0x0 0x1000>;
  191. interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
  192. <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
  193. <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
  194. };
  195. queue-group@2d14000 {
  196. reg = <0x0 0x2d14000 0x0 0x1000>;
  197. interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
  198. <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
  199. <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
  200. };
  201. };
  202. };
  203. ...