mediatek,nand-ecc-engine.yaml 1.4 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: MediaTek(MTK) SoCs NAND ECC engine
  7. maintainers:
  8. - Xiangsheng Hou <xiangsheng.hou@mediatek.com>
  9. description: |
  10. MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller.
  11. properties:
  12. compatible:
  13. enum:
  14. - mediatek,mt2701-ecc
  15. - mediatek,mt2712-ecc
  16. - mediatek,mt7622-ecc
  17. - mediatek,mt7986-ecc
  18. reg:
  19. items:
  20. - description: Base physical address and size of ECC.
  21. interrupts:
  22. items:
  23. - description: ECC interrupt
  24. clocks:
  25. maxItems: 1
  26. clock-names:
  27. const: nfiecc_clk
  28. required:
  29. - compatible
  30. - reg
  31. - interrupts
  32. - clocks
  33. - clock-names
  34. additionalProperties: false
  35. examples:
  36. - |
  37. #include <dt-bindings/clock/mt2701-clk.h>
  38. #include <dt-bindings/interrupt-controller/arm-gic.h>
  39. #include <dt-bindings/interrupt-controller/irq.h>
  40. soc {
  41. #address-cells = <2>;
  42. #size-cells = <2>;
  43. bch: ecc@1100e000 {
  44. compatible = "mediatek,mt2701-ecc";
  45. reg = <0 0x1100e000 0 0x1000>;
  46. interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
  47. clocks = <&pericfg CLK_PERI_NFI_ECC>;
  48. clock-names = "nfiecc_clk";
  49. };
  50. };