max77620.txt 6.1 KB

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  1. MAX77620 Power management IC from Maxim Semiconductor.
  2. Required properties:
  3. -------------------
  4. - compatible: Must be one of
  5. "maxim,max77620"
  6. "maxim,max20024"
  7. "maxim,max77663"
  8. - reg: I2C device address.
  9. Optional properties:
  10. -------------------
  11. - interrupts: The interrupt on the parent the controller is
  12. connected to.
  13. - interrupt-controller: Marks the device node as an interrupt controller.
  14. - #interrupt-cells: is <2> and their usage is compliant to the 2 cells
  15. variant of <../interrupt-controller/interrupts.txt>
  16. IRQ numbers for different interrupt source of MAX77620
  17. are defined at dt-bindings/mfd/max77620.h.
  18. - system-power-controller: Indicates that this PMIC is controlling the
  19. system power, see [1] for more details.
  20. [1] Documentation/devicetree/bindings/power/power-controller.txt
  21. Optional subnodes and their properties:
  22. =======================================
  23. Flexible power sequence configurations:
  24. --------------------------------------
  25. The Flexible Power Sequencer (FPS) allows each regulator to power up under
  26. hardware or software control. Additionally, each regulator can power on
  27. independently or among a group of other regulators with an adjustable power-up
  28. and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can be programmed
  29. to be part of a sequence allowing external regulators to be sequenced along
  30. with internal regulators. 32KHz clock can be programmed to be part of a
  31. sequence.
  32. The flexible sequencing structure consists of two hardware enable inputs
  33. (EN0, EN1), and 3 master sequencing timers called FPS0, FPS1 and FPS2.
  34. Each master sequencing timer is programmable through its configuration
  35. register to have a hardware enable source (EN1 or EN2) or a software enable
  36. source (SW). When enabled/disabled, the master sequencing timer generates
  37. eight sequencing events on different time periods called slots. The time
  38. period between each event is programmable within the configuration register.
  39. Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power
  40. sequence slave register which allows its enable source to be specified as
  41. a flexible power sequencer timer or a software bit. When a FPS source of
  42. regulators, GPIOs and clocks specifies the enable source to be a flexible
  43. power sequencer, the power up and power down delays can be specified in
  44. the regulators, GPIOs and clocks flexible power sequencer configuration
  45. registers.
  46. When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz
  47. clock are set into following state at the sequencing event that
  48. corresponds to its flexible sequencer configuration register.
  49. Sleep state: In this state, regulators, GPIOs
  50. and 32KHz clock get disabled at
  51. the sequencing event.
  52. Global Low Power Mode (GLPM): In this state, regulators are set in
  53. low power mode at the sequencing event.
  54. The configuration parameters of FPS is provided through sub-node "fps"
  55. and their child for FPS specific. The child node name for FPS are "fps0",
  56. "fps1", and "fps2" for FPS0, FPS1 and FPS2 respectively.
  57. The FPS configurations like FPS source, power up and power down slots for
  58. regulators, GPIOs and 32kHz clocks are provided in their respective
  59. configuration nodes which is explained in respective sub-system DT
  60. binding document.
  61. There is need for different FPS configuration parameters based on system
  62. state like when system state changed from active to suspend or active to
  63. power off (shutdown).
  64. Optional properties:
  65. -------------------
  66. -maxim,fps-event-source: u32, FPS event source like external
  67. hardware input to PMIC i.e. EN0, EN1 or
  68. software (SW).
  69. The macros are defined on
  70. dt-bindings/mfd/max77620.h
  71. for different control source.
  72. - MAX77620_FPS_EVENT_SRC_EN0
  73. for hardware input pin EN0.
  74. - MAX77620_FPS_EVENT_SRC_EN1
  75. for hardware input pin EN1.
  76. - MAX77620_FPS_EVENT_SRC_SW
  77. for software control.
  78. -maxim,shutdown-fps-time-period-us: u32, FPS time period in microseconds
  79. when system enters in to shutdown
  80. state.
  81. -maxim,suspend-fps-time-period-us: u32, FPS time period in microseconds
  82. when system enters in to suspend state.
  83. -maxim,device-state-on-disabled-event: u32, describe the PMIC state when FPS
  84. event cleared (set to LOW) whether it
  85. should go to sleep state or low-power
  86. state. Following are valid values:
  87. - MAX77620_FPS_INACTIVE_STATE_SLEEP
  88. to set the PMIC state to sleep.
  89. - MAX77620_FPS_INACTIVE_STATE_LOW_POWER
  90. to set the PMIC state to low
  91. power.
  92. Absence of this property or other value
  93. will not change device state when FPS
  94. event get cleared.
  95. Here supported time periods by device in microseconds are as follows:
  96. MAX77620 supports 40, 80, 160, 320, 640, 1280, 2560 and 5120 microseconds.
  97. MAX20024 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds.
  98. MAX77663 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds.
  99. -maxim,power-ok-control: configure map power ok bit
  100. 1: Enables POK(Power OK) to control nRST_IO and GPIO1
  101. POK function.
  102. 0: Disables POK control.
  103. if property missing, do not configure MPOK bit.
  104. If POK mapping is enabled for GPIO1/nRST_IO then,
  105. GPIO1/nRST_IO pins are HIGH only if all rails
  106. that have POK control enabled are HIGH.
  107. If any of the rails goes down(which are enabled for POK
  108. control) then, GPIO1/nRST_IO goes LOW.
  109. this property is valid for max20024 only.
  110. For DT binding details of different sub modules like GPIO, pincontrol,
  111. regulator, power, please refer respective device-tree binding document
  112. under their respective sub-system directories.
  113. Example:
  114. --------
  115. #include <dt-bindings/mfd/max77620.h>
  116. max77620@3c {
  117. compatible = "maxim,max77620";
  118. reg = <0x3c>;
  119. interrupt-parent = <&intc>;
  120. interrupts = <0 86 IRQ_TYPE_NONE>;
  121. interrupt-controller;
  122. #interrupt-cells = <2>;
  123. fps {
  124. fps0 {
  125. maxim,shutdown-fps-time-period-us = <1280>;
  126. maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
  127. };
  128. fps1 {
  129. maxim,shutdown-fps-time-period-us = <1280>;
  130. maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
  131. };
  132. fps2 {
  133. maxim,shutdown-fps-time-period-us = <1280>;
  134. maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_SW>;
  135. };
  136. };
  137. };