brcm,bcm6368-gpio-sysctl.yaml 5.8 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/mfd/brcm,bcm6368-gpio-sysctl.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Broadcom BCM6368 GPIO System Controller
  7. maintainers:
  8. - Álvaro Fernández Rojas <noltari@gmail.com>
  9. - Jonas Gorski <jonas.gorski@gmail.com>
  10. description:
  11. Broadcom BCM6368 SoC GPIO system controller which provides a register map
  12. for controlling the GPIO and pins of the SoC.
  13. properties:
  14. "#address-cells": true
  15. "#size-cells": true
  16. compatible:
  17. items:
  18. - const: brcm,bcm6368-gpio-sysctl
  19. - const: syscon
  20. - const: simple-mfd
  21. ranges:
  22. maxItems: 1
  23. reg:
  24. maxItems: 1
  25. patternProperties:
  26. "^gpio@[0-9a-f]+$":
  27. # Child node
  28. type: object
  29. $ref: /schemas/gpio/brcm,bcm63xx-gpio.yaml
  30. description:
  31. GPIO controller for the SoC GPIOs. This child node definition
  32. should follow the bindings specified in
  33. Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml.
  34. "^pinctrl@[0-9a-f]+$":
  35. # Child node
  36. type: object
  37. $ref: /schemas/pinctrl/brcm,bcm6368-pinctrl.yaml
  38. description:
  39. Pin controller for the SoC pins. This child node definition
  40. should follow the bindings specified in
  41. Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml.
  42. required:
  43. - "#address-cells"
  44. - compatible
  45. - ranges
  46. - reg
  47. - "#size-cells"
  48. additionalProperties: false
  49. examples:
  50. - |
  51. syscon@10000080 {
  52. #address-cells = <1>;
  53. #size-cells = <1>;
  54. compatible = "brcm,bcm6368-gpio-sysctl", "syscon", "simple-mfd";
  55. reg = <0x10000080 0x80>;
  56. ranges = <0 0x10000080 0x80>;
  57. gpio@0 {
  58. compatible = "brcm,bcm6368-gpio";
  59. reg-names = "dirout", "dat";
  60. reg = <0x0 0x8>, <0x8 0x8>;
  61. gpio-controller;
  62. gpio-ranges = <&pinctrl 0 0 38>;
  63. #gpio-cells = <2>;
  64. };
  65. pinctrl: pinctrl@18 {
  66. compatible = "brcm,bcm6368-pinctrl";
  67. reg = <0x18 0x4>, <0x38 0x4>;
  68. pinctrl_analog_afe_0: analog_afe_0-pins {
  69. function = "analog_afe_0";
  70. pins = "gpio0";
  71. };
  72. pinctrl_analog_afe_1: analog_afe_1-pins {
  73. function = "analog_afe_1";
  74. pins = "gpio1";
  75. };
  76. pinctrl_sys_irq: sys_irq-pins {
  77. function = "sys_irq";
  78. pins = "gpio2";
  79. };
  80. pinctrl_serial_led: serial_led-pins {
  81. pinctrl_serial_led_data: serial_led_data-pins {
  82. function = "serial_led_data";
  83. pins = "gpio3";
  84. };
  85. pinctrl_serial_led_clk: serial_led_clk-pins {
  86. function = "serial_led_clk";
  87. pins = "gpio4";
  88. };
  89. };
  90. pinctrl_inet_led: inet_led-pins {
  91. function = "inet_led";
  92. pins = "gpio5";
  93. };
  94. pinctrl_ephy0_led: ephy0_led-pins {
  95. function = "ephy0_led";
  96. pins = "gpio6";
  97. };
  98. pinctrl_ephy1_led: ephy1_led-pins {
  99. function = "ephy1_led";
  100. pins = "gpio7";
  101. };
  102. pinctrl_ephy2_led: ephy2_led-pins {
  103. function = "ephy2_led";
  104. pins = "gpio8";
  105. };
  106. pinctrl_ephy3_led: ephy3_led-pins {
  107. function = "ephy3_led";
  108. pins = "gpio9";
  109. };
  110. pinctrl_robosw_led_data: robosw_led_data-pins {
  111. function = "robosw_led_data";
  112. pins = "gpio10";
  113. };
  114. pinctrl_robosw_led_clk: robosw_led_clk-pins {
  115. function = "robosw_led_clk";
  116. pins = "gpio11";
  117. };
  118. pinctrl_robosw_led0: robosw_led0-pins {
  119. function = "robosw_led0";
  120. pins = "gpio12";
  121. };
  122. pinctrl_robosw_led1: robosw_led1-pins {
  123. function = "robosw_led1";
  124. pins = "gpio13";
  125. };
  126. pinctrl_usb_device_led: usb_device_led-pins {
  127. function = "usb_device_led";
  128. pins = "gpio14";
  129. };
  130. pinctrl_pci: pci-pins {
  131. pinctrl_pci_req1: pci_req1-pins {
  132. function = "pci_req1";
  133. pins = "gpio16";
  134. };
  135. pinctrl_pci_gnt1: pci_gnt1-pins {
  136. function = "pci_gnt1";
  137. pins = "gpio17";
  138. };
  139. pinctrl_pci_intb: pci_intb-pins {
  140. function = "pci_intb";
  141. pins = "gpio18";
  142. };
  143. pinctrl_pci_req0: pci_req0-pins {
  144. function = "pci_req0";
  145. pins = "gpio19";
  146. };
  147. pinctrl_pci_gnt0: pci_gnt0-pins {
  148. function = "pci_gnt0";
  149. pins = "gpio20";
  150. };
  151. };
  152. pinctrl_pcmcia: pcmcia-pins {
  153. pinctrl_pcmcia_cd1: pcmcia_cd1-pins {
  154. function = "pcmcia_cd1";
  155. pins = "gpio22";
  156. };
  157. pinctrl_pcmcia_cd2: pcmcia_cd2-pins {
  158. function = "pcmcia_cd2";
  159. pins = "gpio23";
  160. };
  161. pinctrl_pcmcia_vs1: pcmcia_vs1-pins {
  162. function = "pcmcia_vs1";
  163. pins = "gpio24";
  164. };
  165. pinctrl_pcmcia_vs2: pcmcia_vs2-pins {
  166. function = "pcmcia_vs2";
  167. pins = "gpio25";
  168. };
  169. };
  170. pinctrl_ebi_cs2: ebi_cs2-pins {
  171. function = "ebi_cs2";
  172. pins = "gpio26";
  173. };
  174. pinctrl_ebi_cs3: ebi_cs3-pins {
  175. function = "ebi_cs3";
  176. pins = "gpio27";
  177. };
  178. pinctrl_spi_cs2: spi_cs2-pins {
  179. function = "spi_cs2";
  180. pins = "gpio28";
  181. };
  182. pinctrl_spi_cs3: spi_cs3-pins {
  183. function = "spi_cs3";
  184. pins = "gpio29";
  185. };
  186. pinctrl_spi_cs4: spi_cs4-pins {
  187. function = "spi_cs4";
  188. pins = "gpio30";
  189. };
  190. pinctrl_spi_cs5: spi_cs5-pins {
  191. function = "spi_cs5";
  192. pins = "gpio31";
  193. };
  194. pinctrl_uart1: uart1-pins {
  195. function = "uart1";
  196. pins = "uart1_grp";
  197. };
  198. };
  199. };