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- # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
- %YAML 1.2
- ---
- $id: http://devicetree.org/schemas/dpll/dpll-pin.yaml#
- $schema: http://devicetree.org/meta-schemas/core.yaml#
- title: DPLL Pin
- maintainers:
- - Ivan Vecera <ivecera@redhat.com>
- description: |
- The DPLL pin is either a physical input or output pin that is provided
- by a DPLL( Digital Phase-Locked Loop) device. The pin is identified by
- its physical order number that is stored in reg property and can have
- an additional set of properties like supported (allowed) frequencies,
- label, type and may support embedded sync.
- Note that the pin in this context has nothing to do with pinctrl.
- properties:
- reg:
- description: Hardware index of the DPLL pin.
- maxItems: 1
- connection-type:
- description: Connection type of the pin
- $ref: /schemas/types.yaml#/definitions/string
- enum: [ext, gnss, int, mux, synce]
- esync-control:
- description: Indicates whether the pin supports embedded sync functionality.
- type: boolean
- label:
- description: String exposed as the pin board label
- $ref: /schemas/types.yaml#/definitions/string
- supported-frequencies-hz:
- description: List of supported frequencies for this pin, expressed in Hz.
- required:
- - reg
- additionalProperties: false
|
