nvidia,tegra20-isp.yaml 1.5 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: NVIDIA Tegra ISP processor
  7. maintainers:
  8. - Thierry Reding <thierry.reding@gmail.com>
  9. - Jon Hunter <jonathanh@nvidia.com>
  10. properties:
  11. compatible:
  12. oneOf:
  13. - enum:
  14. - nvidia,tegra20-isp
  15. - nvidia,tegra30-isp
  16. - nvidia,tegra114-isp
  17. - nvidia,tegra124-isp
  18. - nvidia,tegra210-isp
  19. - items:
  20. - const: nvidia,tegra132-isp
  21. - const: nvidia,tegra124-isp
  22. reg:
  23. maxItems: 1
  24. interrupts:
  25. maxItems: 1
  26. clocks:
  27. items:
  28. - description: module clock
  29. resets:
  30. items:
  31. - description: module reset
  32. reset-names:
  33. items:
  34. - const: isp
  35. iommus:
  36. maxItems: 1
  37. interconnects:
  38. items:
  39. - description: memory write client
  40. interconnect-names:
  41. items:
  42. - const: dma-mem # write
  43. power-domains:
  44. items:
  45. - description: phandle to the VENC or core power domain
  46. additionalProperties: false
  47. examples:
  48. - |
  49. #include <dt-bindings/clock/tegra20-car.h>
  50. #include <dt-bindings/interrupt-controller/arm-gic.h>
  51. isp@54100000 {
  52. compatible = "nvidia,tegra20-isp";
  53. reg = <0x54100000 0x00040000>;
  54. interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  55. clocks = <&tegra_car TEGRA20_CLK_ISP>;
  56. resets = <&tegra_car 23>;
  57. reset-names = "isp";
  58. };