nvidia,tegra20-epp.yaml 1.4 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-epp.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: NVIDIA Tegra Encoder Pre-Processor
  7. maintainers:
  8. - Thierry Reding <thierry.reding@gmail.com>
  9. - Jon Hunter <jonathanh@nvidia.com>
  10. properties:
  11. $nodename:
  12. pattern: "^epp@[0-9a-f]+$"
  13. compatible:
  14. oneOf:
  15. - enum:
  16. - nvidia,tegra20-epp
  17. - nvidia,tegra30-epp
  18. - nvidia,tegra114-epp
  19. - nvidia,tegra124-epp
  20. - items:
  21. - const: nvidia,tegra132-epp
  22. - const: nvidia,tegra124-epp
  23. reg:
  24. maxItems: 1
  25. interrupts:
  26. maxItems: 1
  27. clocks:
  28. maxItems: 1
  29. resets:
  30. items:
  31. - description: module reset
  32. reset-names:
  33. items:
  34. - const: epp
  35. iommus:
  36. maxItems: 1
  37. interconnects:
  38. maxItems: 4
  39. interconnect-names:
  40. maxItems: 4
  41. operating-points-v2: true
  42. power-domains:
  43. items:
  44. - description: phandle to the core power domain
  45. additionalProperties: false
  46. examples:
  47. - |
  48. #include <dt-bindings/clock/tegra20-car.h>
  49. #include <dt-bindings/interrupt-controller/arm-gic.h>
  50. epp@540c0000 {
  51. compatible = "nvidia,tegra20-epp";
  52. reg = <0x540c0000 0x00040000>;
  53. interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  54. clocks = <&tegra_car TEGRA20_CLK_EPP>;
  55. resets = <&tegra_car 19>;
  56. reset-names = "epp";
  57. };