qcom,mdp5.yaml 3.6 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/display/msm/qcom,mdp5.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Qualcomm Adreno/Snapdragon Mobile Display controller (MDP5)
  7. description:
  8. MDP5 display controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994
  9. and MSM8996.
  10. maintainers:
  11. - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  12. - Rob Clark <robdclark@gmail.com>
  13. properties:
  14. compatible:
  15. oneOf:
  16. - const: qcom,mdp5
  17. deprecated: true
  18. - items:
  19. - enum:
  20. - qcom,apq8084-mdp5
  21. - qcom,msm8226-mdp5
  22. - qcom,msm8916-mdp5
  23. - qcom,msm8917-mdp5
  24. - qcom,msm8937-mdp5
  25. - qcom,msm8953-mdp5
  26. - qcom,msm8974-mdp5
  27. - qcom,msm8976-mdp5
  28. - qcom,msm8994-mdp5
  29. - qcom,msm8996-mdp5
  30. - qcom,sdm630-mdp5
  31. - qcom,sdm660-mdp5
  32. - const: qcom,mdp5
  33. $nodename:
  34. pattern: '^display-controller@[0-9a-f]+$'
  35. reg:
  36. maxItems: 1
  37. reg-names:
  38. items:
  39. - const: mdp_phys
  40. interrupts:
  41. maxItems: 1
  42. clocks:
  43. minItems: 4
  44. maxItems: 7
  45. clock-names:
  46. oneOf:
  47. - minItems: 4
  48. items:
  49. - const: iface
  50. - const: bus
  51. - const: core
  52. - const: vsync
  53. - const: tbu
  54. - const: tbu_rt
  55. # MSM8996 has additional iommu clock
  56. - items:
  57. - const: iface
  58. - const: bus
  59. - const: core
  60. - const: iommu
  61. - const: vsync
  62. interconnects:
  63. minItems: 1
  64. items:
  65. - description: Interconnect path from mdp0 (or a single mdp) port to the data bus
  66. - description: Interconnect path from mdp1 port to the data bus
  67. - description: Interconnect path from rotator port to the data bus
  68. interconnect-names:
  69. minItems: 1
  70. items:
  71. - const: mdp0-mem
  72. - const: mdp1-mem
  73. - const: rotator-mem
  74. iommus:
  75. items:
  76. - description: apps SMMU with the Stream-ID mask for Hard-Fail port0
  77. power-domains:
  78. maxItems: 1
  79. operating-points-v2: true
  80. opp-table:
  81. type: object
  82. ports:
  83. $ref: /schemas/graph.yaml#/properties/ports
  84. description: >
  85. Contains the list of output ports from DPU device. These ports
  86. connect to interfaces that are external to the DPU hardware,
  87. such as DSI, DP etc. MDP5 devices support up to 4 ports:
  88. one or two DSI ports, HDMI and eDP.
  89. patternProperties:
  90. "^port@[0-3]+$":
  91. $ref: /schemas/graph.yaml#/properties/port
  92. # at least one port is required
  93. required:
  94. - port@0
  95. required:
  96. - compatible
  97. - reg
  98. - reg-names
  99. - clocks
  100. - clock-names
  101. - ports
  102. additionalProperties: false
  103. examples:
  104. - |
  105. #include <dt-bindings/clock/qcom,gcc-msm8916.h>
  106. #include <dt-bindings/interrupt-controller/arm-gic.h>
  107. display-controller@1a01000 {
  108. compatible = "qcom,mdp5";
  109. reg = <0x1a01000 0x90000>;
  110. reg-names = "mdp_phys";
  111. interrupt-parent = <&mdss>;
  112. interrupts = <0>;
  113. clocks = <&gcc GCC_MDSS_AHB_CLK>,
  114. <&gcc GCC_MDSS_AXI_CLK>,
  115. <&gcc GCC_MDSS_MDP_CLK>,
  116. <&gcc GCC_MDSS_VSYNC_CLK>;
  117. clock-names = "iface",
  118. "bus",
  119. "core",
  120. "vsync";
  121. ports {
  122. #address-cells = <1>;
  123. #size-cells = <0>;
  124. port@0 {
  125. reg = <0>;
  126. endpoint {
  127. remote-endpoint = <&dsi0_in>;
  128. };
  129. };
  130. };
  131. };
  132. ...