dsi-phy-28nm.yaml 1.7 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Qualcomm Display DSI 28nm PHY
  7. maintainers:
  8. - Krishna Manikandan <quic_mkrishn@quicinc.com>
  9. allOf:
  10. - $ref: dsi-phy-common.yaml#
  11. properties:
  12. compatible:
  13. enum:
  14. - qcom,dsi-phy-28nm-8226
  15. - qcom,dsi-phy-28nm-8937
  16. - qcom,dsi-phy-28nm-8960
  17. - qcom,dsi-phy-28nm-hpm
  18. - qcom,dsi-phy-28nm-hpm-fam-b
  19. - qcom,dsi-phy-28nm-lp
  20. reg:
  21. items:
  22. - description: dsi pll register set
  23. - description: dsi phy register set
  24. - description: dsi phy regulator register set
  25. reg-names:
  26. items:
  27. - const: dsi_pll
  28. - const: dsi_phy
  29. - const: dsi_phy_regulator
  30. vddio-supply:
  31. description: Phandle to vdd-io regulator device node.
  32. qcom,dsi-phy-regulator-ldo-mode:
  33. type: boolean
  34. description: Indicates if the LDO mode PHY regulator is wanted.
  35. required:
  36. - compatible
  37. - reg
  38. - reg-names
  39. - vddio-supply
  40. unevaluatedProperties: false
  41. examples:
  42. - |
  43. #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
  44. #include <dt-bindings/clock/qcom,rpmh.h>
  45. dsi-phy@fd922a00 {
  46. compatible = "qcom,dsi-phy-28nm-lp";
  47. reg = <0xfd922a00 0xd4>,
  48. <0xfd922b00 0x2b0>,
  49. <0xfd922d80 0x7b>;
  50. reg-names = "dsi_pll",
  51. "dsi_phy",
  52. "dsi_phy_regulator";
  53. #clock-cells = <1>;
  54. #phy-cells = <0>;
  55. vddio-supply = <&vddio_reg>;
  56. clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
  57. <&rpmhcc RPMH_CXO_CLK>;
  58. clock-names = "iface", "ref";
  59. };
  60. ...