dsi-controller-main.yaml 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489
  1. # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Qualcomm Display DSI controller
  7. maintainers:
  8. - Krishna Manikandan <quic_mkrishn@quicinc.com>
  9. properties:
  10. compatible:
  11. oneOf:
  12. - items:
  13. - enum:
  14. - qcom,apq8064-dsi-ctrl
  15. - qcom,kaanapali-dsi-ctrl
  16. - qcom,msm8226-dsi-ctrl
  17. - qcom,msm8916-dsi-ctrl
  18. - qcom,msm8953-dsi-ctrl
  19. - qcom,msm8974-dsi-ctrl
  20. - qcom,msm8976-dsi-ctrl
  21. - qcom,msm8996-dsi-ctrl
  22. - qcom,msm8998-dsi-ctrl
  23. - qcom,qcm2290-dsi-ctrl
  24. - qcom,sa8775p-dsi-ctrl
  25. - qcom,sar2130p-dsi-ctrl
  26. - qcom,sc7180-dsi-ctrl
  27. - qcom,sc7280-dsi-ctrl
  28. - qcom,sc8180x-dsi-ctrl
  29. - qcom,sdm660-dsi-ctrl
  30. - qcom,sdm670-dsi-ctrl
  31. - qcom,sdm845-dsi-ctrl
  32. - qcom,sm6115-dsi-ctrl
  33. - qcom,sm6125-dsi-ctrl
  34. - qcom,sm6150-dsi-ctrl
  35. - qcom,sm6350-dsi-ctrl
  36. - qcom,sm6375-dsi-ctrl
  37. - qcom,sm7150-dsi-ctrl
  38. - qcom,sm8150-dsi-ctrl
  39. - qcom,sm8250-dsi-ctrl
  40. - qcom,sm8350-dsi-ctrl
  41. - qcom,sm8450-dsi-ctrl
  42. - qcom,sm8550-dsi-ctrl
  43. - qcom,sm8650-dsi-ctrl
  44. - qcom,sm8750-dsi-ctrl
  45. - const: qcom,mdss-dsi-ctrl
  46. - items:
  47. - enum:
  48. - qcom,qcs8300-dsi-ctrl
  49. - const: qcom,sa8775p-dsi-ctrl
  50. - const: qcom,mdss-dsi-ctrl
  51. - enum:
  52. - qcom,dsi-ctrl-6g-qcm2290
  53. - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible
  54. deprecated: true
  55. reg:
  56. maxItems: 1
  57. reg-names:
  58. const: dsi_ctrl
  59. interrupts:
  60. maxItems: 1
  61. clocks:
  62. description: |
  63. Several clocks are used, depending on the variant. Typical ones are::
  64. - bus:: Display AHB clock.
  65. - byte:: Display byte clock.
  66. - byte_intf:: Display byte interface clock.
  67. - core:: Display core clock.
  68. - core_mss:: Core MultiMedia SubSystem clock.
  69. - iface:: Display AXI clock.
  70. - mdp_core:: MDP Core clock.
  71. - mnoc:: MNOC clock
  72. - pixel:: Display pixel clock.
  73. minItems: 3
  74. maxItems: 12
  75. clock-names:
  76. minItems: 3
  77. maxItems: 12
  78. phys:
  79. maxItems: 1
  80. phy-names:
  81. deprecated: true
  82. const: dsi
  83. syscon-sfpb:
  84. description: A phandle to mmss_sfpb syscon node (only for DSIv2).
  85. $ref: /schemas/types.yaml#/definitions/phandle
  86. qcom,dual-dsi-mode:
  87. type: boolean
  88. description: |
  89. Indicates if the DSI controller is driving a panel which needs
  90. 2 DSI links.
  91. qcom,master-dsi:
  92. type: boolean
  93. description: |
  94. Indicates if the DSI controller is the master DSI controller when
  95. qcom,dual-dsi-mode enabled.
  96. qcom,sync-dual-dsi:
  97. type: boolean
  98. description: |
  99. Indicates if the DSI controller needs to sync the other DSI controller
  100. with MIPI DCS commands when qcom,dual-dsi-mode enabled.
  101. assigned-clocks:
  102. minItems: 2
  103. maxItems: 4
  104. description: |
  105. For DSI on SM8650 and older: parents of "byte" and "pixel" for the given
  106. platform.
  107. For DSIv2 platforms this should contain "byte", "esc", "src" and
  108. "pixel_src" clocks.
  109. assigned-clock-parents:
  110. minItems: 2
  111. maxItems: 4
  112. description: |
  113. The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
  114. power-domains:
  115. maxItems: 1
  116. operating-points-v2: true
  117. opp-table:
  118. type: object
  119. ports:
  120. $ref: /schemas/graph.yaml#/properties/ports
  121. description: |
  122. Contains DSI controller input and output ports as children, each
  123. containing one endpoint subnode.
  124. properties:
  125. port@0:
  126. $ref: /schemas/graph.yaml#/$defs/port-base
  127. unevaluatedProperties: false
  128. description: |
  129. Input endpoints of the controller.
  130. properties:
  131. endpoint:
  132. $ref: /schemas/media/video-interfaces.yaml#
  133. unevaluatedProperties: false
  134. properties:
  135. data-lanes:
  136. maxItems: 4
  137. minItems: 1
  138. items:
  139. enum: [ 0, 1, 2, 3 ]
  140. port@1:
  141. $ref: /schemas/graph.yaml#/$defs/port-base
  142. unevaluatedProperties: false
  143. description: |
  144. Output endpoints of the controller.
  145. properties:
  146. endpoint:
  147. $ref: /schemas/media/video-interfaces.yaml#
  148. unevaluatedProperties: false
  149. properties:
  150. data-lanes:
  151. maxItems: 4
  152. minItems: 1
  153. items:
  154. enum: [ 0, 1, 2, 3 ]
  155. qcom,te-source:
  156. $ref: /schemas/types.yaml#/definitions/string
  157. description:
  158. Specifies the source of vsync signal from the panel used for
  159. tearing elimination.
  160. default: mdp_vsync_p
  161. enum:
  162. - mdp_vsync_p
  163. - mdp_vsync_s
  164. - mdp_vsync_e
  165. - timer0
  166. - timer1
  167. - timer2
  168. - timer3
  169. - timer4
  170. required:
  171. - port@0
  172. - port@1
  173. avdd-supply:
  174. description:
  175. Phandle to vdd regulator device node
  176. refgen-supply:
  177. description:
  178. Phandle to REFGEN regulator device node
  179. vcca-supply:
  180. description:
  181. Phandle to vdd regulator device node
  182. vdd-supply:
  183. description:
  184. VDD regulator
  185. vddio-supply:
  186. description:
  187. VDD-IO regulator
  188. vdda-supply:
  189. description:
  190. VDDA regulator
  191. required:
  192. - compatible
  193. - reg
  194. - reg-names
  195. - interrupts
  196. - clocks
  197. - clock-names
  198. - phys
  199. - ports
  200. allOf:
  201. - $ref: ../dsi-controller.yaml#
  202. - if:
  203. properties:
  204. compatible:
  205. contains:
  206. enum:
  207. - qcom,apq8064-dsi-ctrl
  208. then:
  209. properties:
  210. clocks:
  211. minItems: 7
  212. maxItems: 7
  213. clock-names:
  214. items:
  215. - const: iface
  216. - const: bus
  217. - const: core_mmss
  218. - const: src
  219. - const: byte
  220. - const: pixel
  221. - const: core
  222. required:
  223. - assigned-clocks
  224. - assigned-clock-parents
  225. - if:
  226. properties:
  227. compatible:
  228. contains:
  229. enum:
  230. - qcom,msm8916-dsi-ctrl
  231. - qcom,msm8953-dsi-ctrl
  232. - qcom,msm8976-dsi-ctrl
  233. then:
  234. properties:
  235. clocks:
  236. minItems: 6
  237. maxItems: 6
  238. clock-names:
  239. items:
  240. - const: mdp_core
  241. - const: iface
  242. - const: bus
  243. - const: byte
  244. - const: pixel
  245. - const: core
  246. required:
  247. - assigned-clocks
  248. - assigned-clock-parents
  249. - if:
  250. properties:
  251. compatible:
  252. contains:
  253. enum:
  254. - qcom,msm8226-dsi-ctrl
  255. - qcom,msm8974-dsi-ctrl
  256. then:
  257. properties:
  258. clocks:
  259. minItems: 7
  260. maxItems: 7
  261. clock-names:
  262. items:
  263. - const: mdp_core
  264. - const: iface
  265. - const: bus
  266. - const: byte
  267. - const: pixel
  268. - const: core
  269. - const: core_mmss
  270. required:
  271. - assigned-clocks
  272. - assigned-clock-parents
  273. - if:
  274. properties:
  275. compatible:
  276. contains:
  277. enum:
  278. - qcom,msm8996-dsi-ctrl
  279. then:
  280. properties:
  281. clocks:
  282. minItems: 7
  283. maxItems: 7
  284. clock-names:
  285. items:
  286. - const: mdp_core
  287. - const: byte
  288. - const: iface
  289. - const: bus
  290. - const: core_mmss
  291. - const: pixel
  292. - const: core
  293. required:
  294. - assigned-clocks
  295. - assigned-clock-parents
  296. - if:
  297. properties:
  298. compatible:
  299. contains:
  300. enum:
  301. - qcom,msm8998-dsi-ctrl
  302. - qcom,sa8775p-dsi-ctrl
  303. - qcom,sar2130p-dsi-ctrl
  304. - qcom,sc7180-dsi-ctrl
  305. - qcom,sc7280-dsi-ctrl
  306. - qcom,sc8180x-dsi-ctrl
  307. - qcom,sdm845-dsi-ctrl
  308. - qcom,sm6115-dsi-ctrl
  309. - qcom,sm6125-dsi-ctrl
  310. - qcom,sm6350-dsi-ctrl
  311. - qcom,sm6375-dsi-ctrl
  312. - qcom,sm6150-dsi-ctrl
  313. - qcom,sm7150-dsi-ctrl
  314. - qcom,sm8150-dsi-ctrl
  315. - qcom,sm8250-dsi-ctrl
  316. - qcom,sm8350-dsi-ctrl
  317. - qcom,sm8450-dsi-ctrl
  318. - qcom,sm8550-dsi-ctrl
  319. - qcom,sm8650-dsi-ctrl
  320. then:
  321. properties:
  322. clocks:
  323. minItems: 6
  324. maxItems: 6
  325. clock-names:
  326. items:
  327. - const: byte
  328. - const: byte_intf
  329. - const: pixel
  330. - const: core
  331. - const: iface
  332. - const: bus
  333. required:
  334. - assigned-clocks
  335. - assigned-clock-parents
  336. - if:
  337. properties:
  338. compatible:
  339. contains:
  340. enum:
  341. - qcom,kaanapali-dsi-ctrl
  342. - qcom,sm8750-dsi-ctrl
  343. then:
  344. properties:
  345. clocks:
  346. minItems: 12
  347. maxItems: 12
  348. clock-names:
  349. items:
  350. - const: byte
  351. - const: byte_intf
  352. - const: pixel
  353. - const: core
  354. - const: iface
  355. - const: bus
  356. - const: dsi_pll_pixel
  357. - const: dsi_pll_byte
  358. - const: esync
  359. - const: osc
  360. - const: byte_src
  361. - const: pixel_src
  362. - if:
  363. properties:
  364. compatible:
  365. contains:
  366. enum:
  367. - qcom,sdm660-dsi-ctrl
  368. then:
  369. properties:
  370. clocks:
  371. minItems: 9
  372. maxItems: 9
  373. clock-names:
  374. items:
  375. - const: mdp_core
  376. - const: byte
  377. - const: byte_intf
  378. - const: mnoc
  379. - const: iface
  380. - const: bus
  381. - const: core_mmss
  382. - const: pixel
  383. - const: core
  384. required:
  385. - assigned-clocks
  386. - assigned-clock-parents
  387. unevaluatedProperties: false
  388. examples:
  389. - |
  390. #include <dt-bindings/interrupt-controller/arm-gic.h>
  391. #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
  392. #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  393. #include <dt-bindings/power/qcom-rpmpd.h>
  394. dsi@ae94000 {
  395. compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
  396. reg = <0x0ae94000 0x400>;
  397. reg-names = "dsi_ctrl";
  398. #address-cells = <1>;
  399. #size-cells = <0>;
  400. interrupt-parent = <&mdss>;
  401. interrupts = <4>;
  402. clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
  403. <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
  404. <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
  405. <&dispcc DISP_CC_MDSS_ESC0_CLK>,
  406. <&dispcc DISP_CC_MDSS_AHB_CLK>,
  407. <&dispcc DISP_CC_MDSS_AXI_CLK>;
  408. clock-names = "byte",
  409. "byte_intf",
  410. "pixel",
  411. "core",
  412. "iface",
  413. "bus";
  414. phys = <&dsi0_phy>;
  415. phy-names = "dsi";
  416. assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
  417. assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
  418. power-domains = <&rpmhpd SC7180_CX>;
  419. operating-points-v2 = <&dsi_opp_table>;
  420. ports {
  421. #address-cells = <1>;
  422. #size-cells = <0>;
  423. port@0 {
  424. reg = <0>;
  425. endpoint {
  426. remote-endpoint = <&dpu_intf1_out>;
  427. };
  428. };
  429. port@1 {
  430. reg = <1>;
  431. endpoint {
  432. remote-endpoint = <&sn65dsi86_in>;
  433. data-lanes = <0 1 2 3>;
  434. qcom,te-source = "mdp_vsync_e";
  435. };
  436. };
  437. };
  438. };
  439. ...