mediatek,postmask.yaml 3.0 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/display/mediatek/mediatek,postmask.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Mediatek display postmask
  7. maintainers:
  8. - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  9. - Philipp Zabel <p.zabel@pengutronix.de>
  10. description: |
  11. Mediatek display postmask, namely POSTMASK, provides round corner pattern
  12. generation.
  13. POSTMASK device node must be siblings to the central MMSYS_CONFIG node.
  14. For a description of the MMSYS_CONFIG binding, see
  15. Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  16. for details.
  17. properties:
  18. compatible:
  19. oneOf:
  20. - enum:
  21. - mediatek,mt8192-disp-postmask
  22. - items:
  23. - enum:
  24. - mediatek,mt8186-disp-postmask
  25. - mediatek,mt8188-disp-postmask
  26. - const: mediatek,mt8192-disp-postmask
  27. reg:
  28. maxItems: 1
  29. interrupts:
  30. maxItems: 1
  31. power-domains:
  32. description: A phandle and PM domain specifier as defined by bindings of
  33. the power controller specified by phandle. See
  34. Documentation/devicetree/bindings/power/power-domain.yaml for details.
  35. clocks:
  36. items:
  37. - description: POSTMASK Clock
  38. mediatek,gce-client-reg:
  39. description: The register of client driver can be configured by gce with
  40. 4 arguments defined in this property, such as phandle of gce, subsys id,
  41. register offset and size. Each GCE subsys id is mapping to a client
  42. defined in the header include/dt-bindings/gce/<chip>-gce.h.
  43. $ref: /schemas/types.yaml#/definitions/phandle-array
  44. maxItems: 1
  45. ports:
  46. $ref: /schemas/graph.yaml#/properties/ports
  47. description:
  48. Input and output ports can have multiple endpoints, each of those
  49. connects to either the primary, secondary, etc, display pipeline.
  50. properties:
  51. port@0:
  52. $ref: /schemas/graph.yaml#/properties/port
  53. description: POSTMASK input port, usually from GAMMA
  54. port@1:
  55. $ref: /schemas/graph.yaml#/properties/port
  56. description:
  57. POSTMASK output to the input of the next desired component in the
  58. display pipeline, for example one of the available DITHER blocks.
  59. required:
  60. - port@0
  61. - port@1
  62. required:
  63. - compatible
  64. - reg
  65. - interrupts
  66. - power-domains
  67. - clocks
  68. additionalProperties: false
  69. examples:
  70. - |
  71. #include <dt-bindings/interrupt-controller/arm-gic.h>
  72. #include <dt-bindings/clock/mt8192-clk.h>
  73. #include <dt-bindings/power/mt8192-power.h>
  74. #include <dt-bindings/gce/mt8192-gce.h>
  75. soc {
  76. #address-cells = <2>;
  77. #size-cells = <2>;
  78. postmask0: postmask@1400d000 {
  79. compatible = "mediatek,mt8192-disp-postmask";
  80. reg = <0 0x1400d000 0 0x1000>;
  81. interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
  82. power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
  83. clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
  84. mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
  85. };
  86. };