ahci-platform.yaml 4.1 KB

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  1. # SPDX-License-Identifier: GPL-2.0
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: AHCI SATA Controller
  7. description: |
  8. SATA nodes are defined to describe on-chip Serial ATA controllers.
  9. Each SATA controller should have its own node.
  10. It is possible, but not required, to represent each port as a sub-node.
  11. It allows to enable each port independently when dealing with multiple
  12. PHYs.
  13. maintainers:
  14. - Hans de Goede <hdegoede@redhat.com>
  15. - Jens Axboe <axboe@kernel.dk>
  16. properties:
  17. compatible:
  18. oneOf:
  19. - items:
  20. - enum:
  21. - brcm,iproc-ahci
  22. - marvell,armada-8k-ahci
  23. - marvell,berlin2-ahci
  24. - marvell,berlin2q-ahci
  25. - qcom,apq8064-ahci
  26. - qcom,ipq806x-ahci
  27. - socionext,uniphier-pro4-ahci
  28. - socionext,uniphier-pxs2-ahci
  29. - socionext,uniphier-pxs3-ahci
  30. - const: generic-ahci
  31. - enum:
  32. - cavium,octeon-7130-ahci
  33. - hisilicon,hisi-ahci
  34. - ibm,476gtr-ahci
  35. - marvell,armada-3700-ahci
  36. reg:
  37. minItems: 1
  38. maxItems: 2
  39. reg-names:
  40. maxItems: 1
  41. clocks:
  42. minItems: 1
  43. maxItems: 5
  44. clock-names:
  45. minItems: 1
  46. maxItems: 5
  47. interrupts:
  48. maxItems: 1
  49. power-domains:
  50. maxItems: 1
  51. resets:
  52. minItems: 1
  53. maxItems: 3
  54. iommus:
  55. maxItems: 1
  56. patternProperties:
  57. "^sata-port@[0-9a-f]+$":
  58. $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port
  59. anyOf:
  60. - required: [ phys ]
  61. - required: [ target-supply ]
  62. unevaluatedProperties: false
  63. required:
  64. - compatible
  65. - reg
  66. - interrupts
  67. allOf:
  68. - $ref: ahci-common.yaml#
  69. - if:
  70. properties:
  71. compatible:
  72. contains:
  73. enum:
  74. - qcom,apq8064-ahci
  75. - qcom,ipq806x-ahci
  76. then:
  77. properties:
  78. clocks:
  79. minItems: 5
  80. clock-names:
  81. items:
  82. - const: slave_iface
  83. - const: iface
  84. - const: core
  85. - const: rxoob
  86. - const: pmalive
  87. required:
  88. - phys
  89. - phy-names
  90. - clocks
  91. - clock-names
  92. - if:
  93. properties:
  94. compatible:
  95. contains:
  96. const: socionext,uniphier-pro4-ahci
  97. then:
  98. properties:
  99. resets:
  100. items:
  101. - description: reset line for the parent
  102. - description: reset line for the glue logic
  103. - description: reset line for the controller
  104. required:
  105. - resets
  106. else:
  107. if:
  108. properties:
  109. compatible:
  110. contains:
  111. enum:
  112. - socionext,uniphier-pxs2-ahci
  113. - socionext,uniphier-pxs3-ahci
  114. then:
  115. properties:
  116. resets:
  117. items:
  118. - description: reset for the glue logic
  119. - description: reset for the controller
  120. required:
  121. - resets
  122. else:
  123. properties:
  124. resets:
  125. maxItems: 1
  126. unevaluatedProperties: false
  127. examples:
  128. - |
  129. sata@ffe08000 {
  130. compatible = "snps,spear-ahci";
  131. reg = <0xffe08000 0x1000>;
  132. interrupts = <115>;
  133. };
  134. - |
  135. #include <dt-bindings/interrupt-controller/arm-gic.h>
  136. #include <dt-bindings/clock/berlin2q.h>
  137. #include <dt-bindings/ata/ahci.h>
  138. sata@f7e90000 {
  139. compatible = "marvell,berlin2q-ahci", "generic-ahci";
  140. reg = <0xf7e90000 0x1000>;
  141. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  142. clocks = <&chip CLKID_SATA>;
  143. #address-cells = <1>;
  144. #size-cells = <0>;
  145. hba-cap = <HBA_SMPS>;
  146. sata0: sata-port@0 {
  147. reg = <0>;
  148. phys = <&sata_phy 0>;
  149. target-supply = <&reg_sata0>;
  150. hba-port-cap = <(HBA_PORT_FBSCP | HBA_PORT_ESP)>;
  151. };
  152. sata1: sata-port@1 {
  153. reg = <1>;
  154. phys = <&sata_phy 1>;
  155. target-supply = <&reg_sata1>;
  156. hba-port-cap = <(HBA_PORT_HPCP | HBA_PORT_MPSP | HBA_PORT_FBSCP)>;
  157. };
  158. };