pvr2fb.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * drivers/video/pvr2fb.c
  4. *
  5. * Frame buffer and fbcon support for the NEC PowerVR2 found within the Sega
  6. * Dreamcast.
  7. *
  8. * Copyright (c) 2001 M. R. Brown <mrbrown@0xd6.org>
  9. * Copyright (c) 2001 - 2008 Paul Mundt <lethal@linux-sh.org>
  10. *
  11. * This driver is mostly based on the excellent amifb and vfb sources. It uses
  12. * an odd scheme for converting hardware values to/from framebuffer values,
  13. * here are some hacked-up formulas:
  14. *
  15. * The Dreamcast has screen offsets from each side of its four borders and
  16. * the start offsets of the display window. I used these values to calculate
  17. * 'pseudo' values (think of them as placeholders) for the fb video mode, so
  18. * that when it came time to convert these values back into their hardware
  19. * values, I could just add mode- specific offsets to get the correct mode
  20. * settings:
  21. *
  22. * left_margin = diwstart_h - borderstart_h;
  23. * right_margin = borderstop_h - (diwstart_h + xres);
  24. * upper_margin = diwstart_v - borderstart_v;
  25. * lower_margin = borderstop_v - (diwstart_h + yres);
  26. *
  27. * hsync_len = borderstart_h + (hsync_total - borderstop_h);
  28. * vsync_len = borderstart_v + (vsync_total - borderstop_v);
  29. *
  30. * Then, when it's time to convert back to hardware settings, the only
  31. * constants are the borderstart_* offsets, all other values are derived from
  32. * the fb video mode:
  33. *
  34. * // PAL
  35. * borderstart_h = 116;
  36. * borderstart_v = 44;
  37. * ...
  38. * borderstop_h = borderstart_h + hsync_total - hsync_len;
  39. * ...
  40. * diwstart_v = borderstart_v - upper_margin;
  41. *
  42. * However, in the current implementation, the borderstart values haven't had
  43. * the benefit of being fully researched, so some modes may be broken.
  44. */
  45. #undef DEBUG
  46. #include <linux/aperture.h>
  47. #include <linux/module.h>
  48. #include <linux/kernel.h>
  49. #include <linux/errno.h>
  50. #include <linux/string.h>
  51. #include <linux/mm.h>
  52. #include <linux/slab.h>
  53. #include <linux/delay.h>
  54. #include <linux/interrupt.h>
  55. #include <linux/fb.h>
  56. #include <linux/init.h>
  57. #include <linux/pci.h>
  58. #ifdef CONFIG_SH_DREAMCAST
  59. #include <asm/machvec.h>
  60. #include <mach-dreamcast/mach/sysasic.h>
  61. #endif
  62. #ifdef CONFIG_PVR2_DMA
  63. #include <linux/pagemap.h>
  64. #include <mach/dma.h>
  65. #include <asm/dma.h>
  66. #endif
  67. #ifdef CONFIG_SH_STORE_QUEUES
  68. #include <linux/uaccess.h>
  69. #include <cpu/sq.h>
  70. #endif
  71. #ifndef PCI_DEVICE_ID_NEC_NEON250
  72. # define PCI_DEVICE_ID_NEC_NEON250 0x0067
  73. #endif
  74. /* 2D video registers */
  75. #define DISP_BASE par->mmio_base
  76. #define DISP_BRDRCOLR (DISP_BASE + 0x40)
  77. #define DISP_DIWMODE (DISP_BASE + 0x44)
  78. #define DISP_DIWADDRL (DISP_BASE + 0x50)
  79. #define DISP_DIWADDRS (DISP_BASE + 0x54)
  80. #define DISP_DIWSIZE (DISP_BASE + 0x5c)
  81. #define DISP_SYNCCONF (DISP_BASE + 0xd0)
  82. #define DISP_BRDRHORZ (DISP_BASE + 0xd4)
  83. #define DISP_SYNCSIZE (DISP_BASE + 0xd8)
  84. #define DISP_BRDRVERT (DISP_BASE + 0xdc)
  85. #define DISP_DIWCONF (DISP_BASE + 0xe8)
  86. #define DISP_DIWHSTRT (DISP_BASE + 0xec)
  87. #define DISP_DIWVSTRT (DISP_BASE + 0xf0)
  88. #define DISP_PIXDEPTH (DISP_BASE + 0x108)
  89. /* Pixel clocks, one for TV output, doubled for VGA output */
  90. #define TV_CLK 74239
  91. #define VGA_CLK 37119
  92. /* This is for 60Hz - the VTOTAL is doubled for interlaced modes */
  93. #define PAL_HTOTAL 863
  94. #define PAL_VTOTAL 312
  95. #define NTSC_HTOTAL 857
  96. #define NTSC_VTOTAL 262
  97. /* Supported cable types */
  98. enum { CT_VGA, CT_NONE, CT_RGB, CT_COMPOSITE };
  99. /* Supported video output types */
  100. enum { VO_PAL, VO_NTSC, VO_VGA };
  101. /* Supported palette types */
  102. enum { PAL_ARGB1555, PAL_RGB565, PAL_ARGB4444, PAL_ARGB8888 };
  103. struct pvr2_params { unsigned int val; char *name; };
  104. static struct pvr2_params cables[] = {
  105. { CT_VGA, "VGA" }, { CT_RGB, "RGB" }, { CT_COMPOSITE, "COMPOSITE" },
  106. };
  107. static struct pvr2_params outputs[] = {
  108. { VO_PAL, "PAL" }, { VO_NTSC, "NTSC" }, { VO_VGA, "VGA" },
  109. };
  110. /*
  111. * This describes the current video mode
  112. */
  113. static struct pvr2fb_par {
  114. unsigned int hsync_total; /* Clocks/line */
  115. unsigned int vsync_total; /* Lines/field */
  116. unsigned int borderstart_h;
  117. unsigned int borderstop_h;
  118. unsigned int borderstart_v;
  119. unsigned int borderstop_v;
  120. unsigned int diwstart_h; /* Horizontal offset of the display field */
  121. unsigned int diwstart_v; /* Vertical offset of the display field, for
  122. interlaced modes, this is the long field */
  123. unsigned long disp_start; /* Address of image within VRAM */
  124. unsigned char is_interlaced; /* Is the display interlaced? */
  125. unsigned char is_doublescan; /* Are scanlines output twice? (doublescan) */
  126. unsigned char is_lowres; /* Is horizontal pixel-doubling enabled? */
  127. void __iomem *mmio_base; /* MMIO base */
  128. u32 palette[16];
  129. } *currentpar;
  130. static struct fb_info *fb_info;
  131. static struct fb_fix_screeninfo pvr2_fix = {
  132. .id = "NEC PowerVR2",
  133. .type = FB_TYPE_PACKED_PIXELS,
  134. .visual = FB_VISUAL_TRUECOLOR,
  135. .ypanstep = 1,
  136. .ywrapstep = 1,
  137. .accel = FB_ACCEL_NONE,
  138. };
  139. static const struct fb_var_screeninfo pvr2_var = {
  140. .xres = 640,
  141. .yres = 480,
  142. .xres_virtual = 640,
  143. .yres_virtual = 480,
  144. .bits_per_pixel =16,
  145. .red = { 11, 5, 0 },
  146. .green = { 5, 6, 0 },
  147. .blue = { 0, 5, 0 },
  148. .activate = FB_ACTIVATE_NOW,
  149. .height = -1,
  150. .width = -1,
  151. .vmode = FB_VMODE_NONINTERLACED,
  152. };
  153. static int cable_type = CT_VGA;
  154. static int video_output = VO_VGA;
  155. static int nopan = 0;
  156. static int nowrap = 1;
  157. /*
  158. * We do all updating, blanking, etc. during the vertical retrace period
  159. */
  160. static unsigned int do_vmode_full = 0; /* Change the video mode */
  161. static unsigned int do_vmode_pan = 0; /* Update the video mode */
  162. static short do_blank = 0; /* (Un)Blank the screen */
  163. static unsigned int is_blanked = 0; /* Is the screen blanked? */
  164. #ifdef CONFIG_SH_STORE_QUEUES
  165. static unsigned long pvr2fb_map;
  166. #endif
  167. #ifdef CONFIG_PVR2_DMA
  168. static unsigned int shdma = PVR2_CASCADE_CHAN;
  169. static unsigned int pvr2dma = CONFIG_NR_ONCHIP_DMA_CHANNELS;
  170. #endif
  171. static struct fb_videomode pvr2_modedb[] = {
  172. /*
  173. * Broadcast video modes (PAL and NTSC). I'm unfamiliar with
  174. * PAL-M and PAL-N, but from what I've read both modes parallel PAL and
  175. * NTSC, so it shouldn't be a problem (I hope).
  176. */
  177. {
  178. /* 640x480 @ 60Hz interlaced (NTSC) */
  179. "ntsc_640x480i", 60, 640, 480, TV_CLK, 38, 33, 0, 18, 146, 26,
  180. FB_SYNC_BROADCAST, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
  181. }, {
  182. /* 640x240 @ 60Hz (NTSC) */
  183. /* XXX: Broken! Don't use... */
  184. "ntsc_640x240", 60, 640, 240, TV_CLK, 38, 33, 0, 0, 146, 22,
  185. FB_SYNC_BROADCAST, FB_VMODE_YWRAP
  186. }, {
  187. /* 640x480 @ 60hz (VGA) */
  188. "vga_640x480", 60, 640, 480, VGA_CLK, 38, 33, 0, 18, 146, 26,
  189. 0, FB_VMODE_YWRAP
  190. },
  191. };
  192. #define NUM_TOTAL_MODES ARRAY_SIZE(pvr2_modedb)
  193. #define DEFMODE_NTSC 0
  194. #define DEFMODE_PAL 0
  195. #define DEFMODE_VGA 2
  196. static int defmode = DEFMODE_NTSC;
  197. static char *mode_option = NULL;
  198. static inline void pvr2fb_set_pal_type(unsigned int type)
  199. {
  200. struct pvr2fb_par *par = (struct pvr2fb_par *)fb_info->par;
  201. fb_writel(type, par->mmio_base + 0x108);
  202. }
  203. static inline void pvr2fb_set_pal_entry(struct pvr2fb_par *par,
  204. unsigned int regno,
  205. unsigned int val)
  206. {
  207. fb_writel(val, par->mmio_base + 0x1000 + (4 * regno));
  208. }
  209. static int pvr2fb_blank(int blank, struct fb_info *info)
  210. {
  211. do_blank = blank ? blank : -1;
  212. return 0;
  213. }
  214. static inline unsigned long get_line_length(int xres_virtual, int bpp)
  215. {
  216. return (unsigned long)((((xres_virtual*bpp)+31)&~31) >> 3);
  217. }
  218. static void set_color_bitfields(struct fb_var_screeninfo *var)
  219. {
  220. switch (var->bits_per_pixel) {
  221. case 16: /* RGB 565 */
  222. pvr2fb_set_pal_type(PAL_RGB565);
  223. var->red.offset = 11; var->red.length = 5;
  224. var->green.offset = 5; var->green.length = 6;
  225. var->blue.offset = 0; var->blue.length = 5;
  226. var->transp.offset = 0; var->transp.length = 0;
  227. break;
  228. case 24: /* RGB 888 */
  229. var->red.offset = 16; var->red.length = 8;
  230. var->green.offset = 8; var->green.length = 8;
  231. var->blue.offset = 0; var->blue.length = 8;
  232. var->transp.offset = 0; var->transp.length = 0;
  233. break;
  234. case 32: /* ARGB 8888 */
  235. pvr2fb_set_pal_type(PAL_ARGB8888);
  236. var->red.offset = 16; var->red.length = 8;
  237. var->green.offset = 8; var->green.length = 8;
  238. var->blue.offset = 0; var->blue.length = 8;
  239. var->transp.offset = 24; var->transp.length = 8;
  240. break;
  241. }
  242. }
  243. static int pvr2fb_setcolreg(unsigned int regno, unsigned int red,
  244. unsigned int green, unsigned int blue,
  245. unsigned int transp, struct fb_info *info)
  246. {
  247. struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
  248. unsigned int tmp;
  249. if (regno > info->cmap.len)
  250. return 1;
  251. /*
  252. * We only support the hardware palette for 16 and 32bpp. It's also
  253. * expected that the palette format has been set by the time we get
  254. * here, so we don't waste time setting it again.
  255. */
  256. switch (info->var.bits_per_pixel) {
  257. case 16: /* RGB 565 */
  258. tmp = (red & 0xf800) |
  259. ((green & 0xfc00) >> 5) |
  260. ((blue & 0xf800) >> 11);
  261. pvr2fb_set_pal_entry(par, regno, tmp);
  262. break;
  263. case 24: /* RGB 888 */
  264. red >>= 8; green >>= 8; blue >>= 8;
  265. tmp = (red << 16) | (green << 8) | blue;
  266. break;
  267. case 32: /* ARGB 8888 */
  268. red >>= 8; green >>= 8; blue >>= 8;
  269. tmp = (transp << 24) | (red << 16) | (green << 8) | blue;
  270. pvr2fb_set_pal_entry(par, regno, tmp);
  271. break;
  272. default:
  273. pr_debug("Invalid bit depth %d?!?\n", info->var.bits_per_pixel);
  274. return 1;
  275. }
  276. if (regno < 16)
  277. ((u32*)(info->pseudo_palette))[regno] = tmp;
  278. return 0;
  279. }
  280. /*
  281. * Determine the cable type and initialize the cable output format. Don't do
  282. * anything if the cable type has been overidden (via "cable:XX").
  283. */
  284. #define PCTRA ((void __iomem *)0xff80002c)
  285. #define PDTRA ((void __iomem *)0xff800030)
  286. #define VOUTC ((void __iomem *)0xa0702c00)
  287. static int pvr2_init_cable(void)
  288. {
  289. if (cable_type < 0) {
  290. fb_writel((fb_readl(PCTRA) & 0xfff0ffff) | 0x000a0000,
  291. PCTRA);
  292. cable_type = (fb_readw(PDTRA) >> 8) & 3;
  293. }
  294. /* Now select the output format (either composite or other) */
  295. /* XXX: Save the previous val first, as this reg is also AICA
  296. related */
  297. if (cable_type == CT_COMPOSITE)
  298. fb_writel(3 << 8, VOUTC);
  299. else if (cable_type == CT_RGB)
  300. fb_writel(1 << 9, VOUTC);
  301. else
  302. fb_writel(0, VOUTC);
  303. return cable_type;
  304. }
  305. static int pvr2fb_set_par(struct fb_info *info)
  306. {
  307. struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
  308. struct fb_var_screeninfo *var = &info->var;
  309. unsigned long line_length;
  310. unsigned int vtotal;
  311. /*
  312. * XXX: It's possible that a user could use a VGA box, change the cable
  313. * type in hardware (i.e. switch from VGA<->composite), then change
  314. * modes (i.e. switching to another VT). If that happens we should
  315. * automagically change the output format to cope, but currently I
  316. * don't have a VGA box to make sure this works properly.
  317. */
  318. cable_type = pvr2_init_cable();
  319. if (cable_type == CT_VGA && video_output != VO_VGA)
  320. video_output = VO_VGA;
  321. var->vmode &= FB_VMODE_MASK;
  322. if (var->vmode & FB_VMODE_INTERLACED && video_output != VO_VGA)
  323. par->is_interlaced = 1;
  324. /*
  325. * XXX: Need to be more creative with this (i.e. allow doublecan for
  326. * PAL/NTSC output).
  327. */
  328. if (var->vmode & FB_VMODE_DOUBLE && video_output == VO_VGA)
  329. par->is_doublescan = 1;
  330. par->hsync_total = var->left_margin + var->xres + var->right_margin +
  331. var->hsync_len;
  332. par->vsync_total = var->upper_margin + var->yres + var->lower_margin +
  333. var->vsync_len;
  334. if (var->sync & FB_SYNC_BROADCAST) {
  335. vtotal = par->vsync_total;
  336. if (par->is_interlaced)
  337. vtotal /= 2;
  338. if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
  339. /* XXX: Check for start values here... */
  340. /* XXX: Check hardware for PAL-compatibility */
  341. par->borderstart_h = 116;
  342. par->borderstart_v = 44;
  343. } else {
  344. /* NTSC video output */
  345. par->borderstart_h = 126;
  346. par->borderstart_v = 18;
  347. }
  348. } else {
  349. /* VGA mode */
  350. /* XXX: What else needs to be checked? */
  351. /*
  352. * XXX: We have a little freedom in VGA modes, what ranges
  353. * should be here (i.e. hsync/vsync totals, etc.)?
  354. */
  355. par->borderstart_h = 126;
  356. par->borderstart_v = 40;
  357. }
  358. /* Calculate the remainding offsets */
  359. par->diwstart_h = par->borderstart_h + var->left_margin;
  360. par->diwstart_v = par->borderstart_v + var->upper_margin;
  361. par->borderstop_h = par->diwstart_h + var->xres +
  362. var->right_margin;
  363. par->borderstop_v = par->diwstart_v + var->yres +
  364. var->lower_margin;
  365. if (!par->is_interlaced)
  366. par->borderstop_v /= 2;
  367. if (info->var.xres < 640)
  368. par->is_lowres = 1;
  369. line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
  370. par->disp_start = info->fix.smem_start + (line_length * var->yoffset) * line_length;
  371. info->fix.line_length = line_length;
  372. return 0;
  373. }
  374. static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  375. {
  376. struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
  377. unsigned int vtotal, hsync_total;
  378. unsigned long line_length;
  379. if (var->pixclock != TV_CLK && var->pixclock != VGA_CLK) {
  380. pr_debug("Invalid pixclock value %d\n", var->pixclock);
  381. return -EINVAL;
  382. }
  383. if (var->xres < 320)
  384. var->xres = 320;
  385. if (var->yres < 240)
  386. var->yres = 240;
  387. if (var->xres_virtual < var->xres)
  388. var->xres_virtual = var->xres;
  389. if (var->yres_virtual < var->yres)
  390. var->yres_virtual = var->yres;
  391. if (var->bits_per_pixel <= 16)
  392. var->bits_per_pixel = 16;
  393. else if (var->bits_per_pixel <= 24)
  394. var->bits_per_pixel = 24;
  395. else if (var->bits_per_pixel <= 32)
  396. var->bits_per_pixel = 32;
  397. set_color_bitfields(var);
  398. if (var->vmode & FB_VMODE_YWRAP) {
  399. if (var->xoffset || var->yoffset >= var->yres_virtual) {
  400. var->xoffset = var->yoffset = 0;
  401. } else {
  402. if (var->xoffset > var->xres_virtual - var->xres ||
  403. var->yoffset > var->yres_virtual - var->yres)
  404. var->xoffset = var->yoffset = 0;
  405. }
  406. } else {
  407. var->xoffset = var->yoffset = 0;
  408. }
  409. /*
  410. * XXX: Need to be more creative with this (i.e. allow doublecan for
  411. * PAL/NTSC output).
  412. */
  413. if (var->yres < 480 && video_output == VO_VGA)
  414. var->vmode |= FB_VMODE_DOUBLE;
  415. if (video_output != VO_VGA) {
  416. var->sync |= FB_SYNC_BROADCAST;
  417. var->vmode |= FB_VMODE_INTERLACED;
  418. } else {
  419. var->sync &= ~FB_SYNC_BROADCAST;
  420. var->vmode &= ~FB_VMODE_INTERLACED;
  421. var->vmode |= FB_VMODE_NONINTERLACED;
  422. }
  423. if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_TEST) {
  424. var->right_margin = par->borderstop_h -
  425. (par->diwstart_h + var->xres);
  426. var->left_margin = par->diwstart_h - par->borderstart_h;
  427. var->hsync_len = par->borderstart_h +
  428. (par->hsync_total - par->borderstop_h);
  429. var->upper_margin = par->diwstart_v - par->borderstart_v;
  430. var->lower_margin = par->borderstop_v -
  431. (par->diwstart_v + var->yres);
  432. var->vsync_len = par->borderstop_v +
  433. (par->vsync_total - par->borderstop_v);
  434. }
  435. hsync_total = var->left_margin + var->xres + var->right_margin +
  436. var->hsync_len;
  437. vtotal = var->upper_margin + var->yres + var->lower_margin +
  438. var->vsync_len;
  439. if (var->sync & FB_SYNC_BROADCAST) {
  440. if (var->vmode & FB_VMODE_INTERLACED)
  441. vtotal /= 2;
  442. if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
  443. /* PAL video output */
  444. /* XXX: Should be using a range here ... ? */
  445. if (hsync_total != PAL_HTOTAL) {
  446. pr_debug("invalid hsync total for PAL\n");
  447. return -EINVAL;
  448. }
  449. } else {
  450. /* NTSC video output */
  451. if (hsync_total != NTSC_HTOTAL) {
  452. pr_debug("invalid hsync total for NTSC\n");
  453. return -EINVAL;
  454. }
  455. }
  456. }
  457. /* Check memory sizes */
  458. line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
  459. if (line_length * var->yres_virtual > info->fix.smem_len)
  460. return -ENOMEM;
  461. return 0;
  462. }
  463. static void pvr2_update_display(struct fb_info *info)
  464. {
  465. struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
  466. struct fb_var_screeninfo *var = &info->var;
  467. /* Update the start address of the display image */
  468. fb_writel(par->disp_start, DISP_DIWADDRL);
  469. fb_writel(par->disp_start +
  470. get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
  471. DISP_DIWADDRS);
  472. }
  473. /*
  474. * Initialize the video mode. Currently, the 16bpp and 24bpp modes aren't
  475. * very stable. It's probably due to the fact that a lot of the 2D video
  476. * registers are still undocumented.
  477. */
  478. static void pvr2_init_display(struct fb_info *info)
  479. {
  480. struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
  481. struct fb_var_screeninfo *var = &info->var;
  482. unsigned int diw_height, diw_width, diw_modulo = 1;
  483. unsigned int bytesperpixel = var->bits_per_pixel >> 3;
  484. /* hsync and vsync totals */
  485. fb_writel((par->vsync_total << 16) | par->hsync_total, DISP_SYNCSIZE);
  486. /* column height, modulo, row width */
  487. /* since we're "panning" within vram, we need to offset things based
  488. * on the offset from the virtual x start to our real gfx. */
  489. if (video_output != VO_VGA && par->is_interlaced)
  490. diw_modulo += info->fix.line_length / 4;
  491. diw_height = (par->is_interlaced ? var->yres / 2 : var->yres);
  492. diw_width = get_line_length(var->xres, var->bits_per_pixel) / 4;
  493. fb_writel((diw_modulo << 20) | (--diw_height << 10) | --diw_width,
  494. DISP_DIWSIZE);
  495. /* display address, long and short fields */
  496. fb_writel(par->disp_start, DISP_DIWADDRL);
  497. fb_writel(par->disp_start +
  498. get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
  499. DISP_DIWADDRS);
  500. /* border horizontal, border vertical, border color */
  501. fb_writel((par->borderstart_h << 16) | par->borderstop_h, DISP_BRDRHORZ);
  502. fb_writel((par->borderstart_v << 16) | par->borderstop_v, DISP_BRDRVERT);
  503. fb_writel(0, DISP_BRDRCOLR);
  504. /* display window start position */
  505. fb_writel(par->diwstart_h, DISP_DIWHSTRT);
  506. fb_writel((par->diwstart_v << 16) | par->diwstart_v, DISP_DIWVSTRT);
  507. /* misc. settings */
  508. fb_writel((0x16 << 16) | par->is_lowres, DISP_DIWCONF);
  509. /* clock doubler (for VGA), scan doubler, display enable */
  510. fb_writel(((video_output == VO_VGA) << 23) |
  511. (par->is_doublescan << 1) | 1, DISP_DIWMODE);
  512. /* bits per pixel */
  513. fb_writel(fb_readl(DISP_DIWMODE) | (--bytesperpixel << 2), DISP_DIWMODE);
  514. fb_writel(bytesperpixel << 2, DISP_PIXDEPTH);
  515. /* video enable, color sync, interlace,
  516. * hsync and vsync polarity (currently unused) */
  517. fb_writel(0x100 | ((par->is_interlaced /*|4*/) << 4), DISP_SYNCCONF);
  518. }
  519. /* Simulate blanking by making the border cover the entire screen */
  520. #define BLANK_BIT (1<<3)
  521. static void pvr2_do_blank(void)
  522. {
  523. struct pvr2fb_par *par = currentpar;
  524. unsigned long diwconf;
  525. diwconf = fb_readl(DISP_DIWCONF);
  526. if (do_blank > 0)
  527. fb_writel(diwconf | BLANK_BIT, DISP_DIWCONF);
  528. else
  529. fb_writel(diwconf & ~BLANK_BIT, DISP_DIWCONF);
  530. is_blanked = do_blank > 0 ? do_blank : 0;
  531. }
  532. static irqreturn_t __maybe_unused pvr2fb_interrupt(int irq, void *dev_id)
  533. {
  534. struct fb_info *info = dev_id;
  535. if (do_vmode_pan || do_vmode_full)
  536. pvr2_update_display(info);
  537. if (do_vmode_full)
  538. pvr2_init_display(info);
  539. if (do_vmode_pan)
  540. do_vmode_pan = 0;
  541. if (do_vmode_full)
  542. do_vmode_full = 0;
  543. if (do_blank) {
  544. pvr2_do_blank();
  545. do_blank = 0;
  546. }
  547. return IRQ_HANDLED;
  548. }
  549. #ifdef CONFIG_PVR2_DMA
  550. static ssize_t pvr2fb_write(struct fb_info *info, const char *buf,
  551. size_t count, loff_t *ppos)
  552. {
  553. unsigned long dst, start, end, len;
  554. unsigned int nr_pages;
  555. struct page **pages;
  556. int ret, i;
  557. if (!info->screen_base)
  558. return -ENODEV;
  559. nr_pages = (count + PAGE_SIZE - 1) >> PAGE_SHIFT;
  560. pages = kmalloc_objs(struct page *, nr_pages);
  561. if (!pages)
  562. return -ENOMEM;
  563. ret = pin_user_pages_fast((unsigned long)buf, nr_pages, FOLL_WRITE, pages);
  564. if (ret < nr_pages) {
  565. if (ret < 0) {
  566. /*
  567. * Clamp the unsigned nr_pages to zero so that the
  568. * error handling works. And leave ret at whatever
  569. * -errno value was returned from GUP.
  570. */
  571. nr_pages = 0;
  572. } else {
  573. nr_pages = ret;
  574. /*
  575. * Use -EINVAL to represent a mildly desperate guess at
  576. * why we got fewer pages (maybe even zero pages) than
  577. * requested.
  578. */
  579. ret = -EINVAL;
  580. }
  581. goto out_unmap;
  582. }
  583. dma_configure_channel(shdma, 0x12c1);
  584. dst = (unsigned long)fb_info->screen_base + *ppos;
  585. start = (unsigned long)page_address(pages[0]);
  586. end = (unsigned long)page_address(pages[nr_pages]);
  587. len = nr_pages << PAGE_SHIFT;
  588. /* Half-assed contig check */
  589. if (start + len == end) {
  590. /* As we do this in one shot, it's either all or nothing.. */
  591. if ((*ppos + len) > fb_info->fix.smem_len) {
  592. ret = -ENOSPC;
  593. goto out_unmap;
  594. }
  595. dma_write(shdma, start, 0, len);
  596. dma_write(pvr2dma, 0, dst, len);
  597. dma_wait_for_completion(pvr2dma);
  598. goto out;
  599. }
  600. /* Not contiguous, writeout per-page instead.. */
  601. for (i = 0; i < nr_pages; i++, dst += PAGE_SIZE) {
  602. if ((*ppos + (i << PAGE_SHIFT)) > fb_info->fix.smem_len) {
  603. ret = -ENOSPC;
  604. goto out_unmap;
  605. }
  606. dma_write_page(shdma, (unsigned long)page_address(pages[i]), 0);
  607. dma_write_page(pvr2dma, 0, dst);
  608. dma_wait_for_completion(pvr2dma);
  609. }
  610. out:
  611. *ppos += count;
  612. ret = count;
  613. out_unmap:
  614. unpin_user_pages(pages, nr_pages);
  615. kfree(pages);
  616. return ret;
  617. }
  618. #endif /* CONFIG_PVR2_DMA */
  619. static const struct fb_ops pvr2fb_ops = {
  620. .owner = THIS_MODULE,
  621. #ifdef CONFIG_PVR2_DMA
  622. .fb_read = fb_io_read,
  623. .fb_write = pvr2fb_write,
  624. #else
  625. __FB_DEFAULT_IOMEM_OPS_RDWR,
  626. #endif
  627. .fb_setcolreg = pvr2fb_setcolreg,
  628. .fb_blank = pvr2fb_blank,
  629. __FB_DEFAULT_IOMEM_OPS_DRAW,
  630. .fb_check_var = pvr2fb_check_var,
  631. .fb_set_par = pvr2fb_set_par,
  632. __FB_DEFAULT_IOMEM_OPS_MMAP,
  633. };
  634. #ifndef MODULE
  635. static int pvr2_get_param_val(const struct pvr2_params *p, const char *s,
  636. int size)
  637. {
  638. int i;
  639. for (i = 0; i < size; i++) {
  640. if (!strncasecmp(p[i].name, s, strlen(s)))
  641. return p[i].val;
  642. }
  643. return -1;
  644. }
  645. #endif
  646. static char *pvr2_get_param_name(const struct pvr2_params *p, int val,
  647. int size)
  648. {
  649. int i;
  650. for (i = 0; i < size; i++) {
  651. if (p[i].val == val)
  652. return p[i].name;
  653. }
  654. return NULL;
  655. }
  656. /**
  657. * pvr2fb_common_init
  658. *
  659. * Common init code for the PVR2 chips.
  660. *
  661. * This mostly takes care of the common aspects of the fb setup and
  662. * registration. It's expected that the board-specific init code has
  663. * already setup pvr2_fix with something meaningful at this point.
  664. *
  665. * Device info reporting is also done here, as well as picking a sane
  666. * default from the modedb. For board-specific modelines, simply define
  667. * a per-board modedb.
  668. *
  669. * Also worth noting is that the cable and video output types are likely
  670. * always going to be VGA for the PCI-based PVR2 boards, but we leave this
  671. * in for flexibility anyways. Who knows, maybe someone has tv-out on a
  672. * PCI-based version of these things ;-)
  673. */
  674. static int __maybe_unused pvr2fb_common_init(void)
  675. {
  676. struct pvr2fb_par *par = currentpar;
  677. unsigned long modememused, rev;
  678. fb_info->screen_base = ioremap(pvr2_fix.smem_start,
  679. pvr2_fix.smem_len);
  680. if (!fb_info->screen_base) {
  681. printk(KERN_ERR "pvr2fb: Failed to remap smem space\n");
  682. goto out_err;
  683. }
  684. par->mmio_base = ioremap(pvr2_fix.mmio_start,
  685. pvr2_fix.mmio_len);
  686. if (!par->mmio_base) {
  687. printk(KERN_ERR "pvr2fb: Failed to remap mmio space\n");
  688. goto out_err;
  689. }
  690. fb_memset_io(fb_info->screen_base, 0, pvr2_fix.smem_len);
  691. pvr2_fix.ypanstep = nopan ? 0 : 1;
  692. pvr2_fix.ywrapstep = nowrap ? 0 : 1;
  693. fb_info->fbops = &pvr2fb_ops;
  694. fb_info->fix = pvr2_fix;
  695. fb_info->par = currentpar;
  696. fb_info->pseudo_palette = currentpar->palette;
  697. fb_info->flags = FBINFO_HWACCEL_YPAN;
  698. if (video_output == VO_VGA)
  699. defmode = DEFMODE_VGA;
  700. if (!mode_option)
  701. mode_option = "640x480@60";
  702. if (!fb_find_mode(&fb_info->var, fb_info, mode_option, pvr2_modedb,
  703. NUM_TOTAL_MODES, &pvr2_modedb[defmode], 16))
  704. fb_info->var = pvr2_var;
  705. fb_alloc_cmap(&fb_info->cmap, 256, 0);
  706. if (register_framebuffer(fb_info) < 0)
  707. goto out_err;
  708. /*Must write PIXDEPTH to register before anything is displayed - so force init */
  709. pvr2_init_display(fb_info);
  710. modememused = get_line_length(fb_info->var.xres_virtual,
  711. fb_info->var.bits_per_pixel);
  712. modememused *= fb_info->var.yres_virtual;
  713. rev = fb_readl(par->mmio_base + 0x04);
  714. fb_info(fb_info, "%s (rev %ld.%ld) frame buffer device, using %ldk/%ldk of video memory\n",
  715. fb_info->fix.id, (rev >> 4) & 0x0f, rev & 0x0f,
  716. modememused >> 10,
  717. (unsigned long)(fb_info->fix.smem_len >> 10));
  718. fb_info(fb_info, "Mode %dx%d-%d pitch = %ld cable: %s video output: %s\n",
  719. fb_info->var.xres, fb_info->var.yres,
  720. fb_info->var.bits_per_pixel,
  721. get_line_length(fb_info->var.xres, fb_info->var.bits_per_pixel),
  722. pvr2_get_param_name(cables, cable_type, 3),
  723. pvr2_get_param_name(outputs, video_output, 3));
  724. #ifdef CONFIG_SH_STORE_QUEUES
  725. fb_notice(fb_info, "registering with SQ API\n");
  726. pvr2fb_map = sq_remap(fb_info->fix.smem_start, fb_info->fix.smem_len,
  727. fb_info->fix.id, PAGE_SHARED);
  728. fb_notice(fb_info, "Mapped video memory to SQ addr 0x%lx\n",
  729. pvr2fb_map);
  730. #endif
  731. return 0;
  732. out_err:
  733. if (fb_info->screen_base)
  734. iounmap(fb_info->screen_base);
  735. if (par->mmio_base)
  736. iounmap(par->mmio_base);
  737. return -ENXIO;
  738. }
  739. #ifdef CONFIG_SH_DREAMCAST
  740. static int __init pvr2fb_dc_init(void)
  741. {
  742. if (!mach_is_dreamcast())
  743. return -ENXIO;
  744. /* Make a guess at the monitor based on the attached cable */
  745. if (pvr2_init_cable() == CT_VGA) {
  746. fb_info->monspecs.hfmin = 30000;
  747. fb_info->monspecs.hfmax = 70000;
  748. fb_info->monspecs.vfmin = 60;
  749. fb_info->monspecs.vfmax = 60;
  750. } else {
  751. /* Not VGA, using a TV (taken from acornfb) */
  752. fb_info->monspecs.hfmin = 15469;
  753. fb_info->monspecs.hfmax = 15781;
  754. fb_info->monspecs.vfmin = 49;
  755. fb_info->monspecs.vfmax = 51;
  756. }
  757. /*
  758. * XXX: This needs to pull default video output via BIOS or other means
  759. */
  760. if (video_output < 0) {
  761. if (cable_type == CT_VGA) {
  762. video_output = VO_VGA;
  763. } else {
  764. video_output = VO_NTSC;
  765. }
  766. }
  767. /*
  768. * Nothing exciting about the DC PVR2 .. only a measly 8MiB.
  769. */
  770. pvr2_fix.smem_start = 0xa5000000; /* RAM starts here */
  771. pvr2_fix.smem_len = 8 << 20;
  772. pvr2_fix.mmio_start = 0xa05f8000; /* registers start here */
  773. pvr2_fix.mmio_len = 0x2000;
  774. if (request_irq(HW_EVENT_VSYNC, pvr2fb_interrupt, IRQF_SHARED,
  775. "pvr2 VBL handler", fb_info)) {
  776. return -EBUSY;
  777. }
  778. #ifdef CONFIG_PVR2_DMA
  779. if (request_dma(pvr2dma, "pvr2") != 0) {
  780. free_irq(HW_EVENT_VSYNC, fb_info);
  781. return -EBUSY;
  782. }
  783. #endif
  784. return pvr2fb_common_init();
  785. }
  786. static void pvr2fb_dc_exit(void)
  787. {
  788. if (fb_info->screen_base) {
  789. iounmap(fb_info->screen_base);
  790. fb_info->screen_base = NULL;
  791. }
  792. if (currentpar->mmio_base) {
  793. iounmap(currentpar->mmio_base);
  794. currentpar->mmio_base = NULL;
  795. }
  796. free_irq(HW_EVENT_VSYNC, fb_info);
  797. #ifdef CONFIG_PVR2_DMA
  798. free_dma(pvr2dma);
  799. #endif
  800. }
  801. #endif /* CONFIG_SH_DREAMCAST */
  802. #ifdef CONFIG_PCI
  803. static int pvr2fb_pci_probe(struct pci_dev *pdev,
  804. const struct pci_device_id *ent)
  805. {
  806. int ret;
  807. ret = aperture_remove_conflicting_pci_devices(pdev, "pvrfb");
  808. if (ret)
  809. return ret;
  810. ret = pci_enable_device(pdev);
  811. if (ret) {
  812. printk(KERN_ERR "pvr2fb: PCI enable failed\n");
  813. return ret;
  814. }
  815. ret = pci_request_regions(pdev, "pvr2fb");
  816. if (ret) {
  817. printk(KERN_ERR "pvr2fb: PCI request regions failed\n");
  818. return ret;
  819. }
  820. /*
  821. * Slightly more exciting than the DC PVR2 .. 16MiB!
  822. */
  823. pvr2_fix.smem_start = pci_resource_start(pdev, 0);
  824. pvr2_fix.smem_len = pci_resource_len(pdev, 0);
  825. pvr2_fix.mmio_start = pci_resource_start(pdev, 1);
  826. pvr2_fix.mmio_len = pci_resource_len(pdev, 1);
  827. fb_info->device = &pdev->dev;
  828. return pvr2fb_common_init();
  829. }
  830. static void pvr2fb_pci_remove(struct pci_dev *pdev)
  831. {
  832. if (fb_info->screen_base) {
  833. iounmap(fb_info->screen_base);
  834. fb_info->screen_base = NULL;
  835. }
  836. if (currentpar->mmio_base) {
  837. iounmap(currentpar->mmio_base);
  838. currentpar->mmio_base = NULL;
  839. }
  840. pci_release_regions(pdev);
  841. }
  842. static const struct pci_device_id pvr2fb_pci_tbl[] = {
  843. { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NEON250,
  844. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  845. { 0, },
  846. };
  847. MODULE_DEVICE_TABLE(pci, pvr2fb_pci_tbl);
  848. static struct pci_driver pvr2fb_pci_driver = {
  849. .name = "pvr2fb",
  850. .id_table = pvr2fb_pci_tbl,
  851. .probe = pvr2fb_pci_probe,
  852. .remove = pvr2fb_pci_remove,
  853. };
  854. static int __init pvr2fb_pci_init(void)
  855. {
  856. return pci_register_driver(&pvr2fb_pci_driver);
  857. }
  858. static void pvr2fb_pci_exit(void)
  859. {
  860. pci_unregister_driver(&pvr2fb_pci_driver);
  861. }
  862. #endif /* CONFIG_PCI */
  863. /*
  864. * Parse command arguments. Supported arguments are:
  865. * inverse Use inverse color maps
  866. * cable:composite|rgb|vga Override the video cable type
  867. * output:NTSC|PAL|VGA Override the video output format
  868. *
  869. * <xres>x<yres>[-<bpp>][@<refresh>] or,
  870. * <name>[-<bpp>][@<refresh>] Startup using this video mode
  871. */
  872. #ifndef MODULE
  873. static int __init pvr2fb_setup(char *options)
  874. {
  875. char *this_opt;
  876. char cable_arg[80];
  877. char output_arg[80];
  878. if (!options || !*options)
  879. return 0;
  880. cable_arg[0] = output_arg[0] = 0;
  881. while ((this_opt = strsep(&options, ","))) {
  882. if (!*this_opt)
  883. continue;
  884. if (!strcmp(this_opt, "inverse")) {
  885. fb_invert_cmaps();
  886. } else if (!strncmp(this_opt, "cable:", 6)) {
  887. strcpy(cable_arg, this_opt + 6);
  888. } else if (!strncmp(this_opt, "output:", 7)) {
  889. strcpy(output_arg, this_opt + 7);
  890. } else if (!strncmp(this_opt, "nopan", 5)) {
  891. nopan = 1;
  892. } else if (!strncmp(this_opt, "nowrap", 6)) {
  893. nowrap = 1;
  894. } else {
  895. mode_option = this_opt;
  896. }
  897. }
  898. if (*cable_arg)
  899. cable_type = pvr2_get_param_val(cables, cable_arg, 3);
  900. if (*output_arg)
  901. video_output = pvr2_get_param_val(outputs, output_arg, 3);
  902. return 0;
  903. }
  904. #endif
  905. static struct pvr2_board {
  906. int (*init)(void);
  907. void (*exit)(void);
  908. char name[16];
  909. } board_driver[] __refdata = {
  910. #ifdef CONFIG_SH_DREAMCAST
  911. { pvr2fb_dc_init, pvr2fb_dc_exit, "Sega DC PVR2" },
  912. #endif
  913. #ifdef CONFIG_PCI
  914. { pvr2fb_pci_init, pvr2fb_pci_exit, "PCI PVR2" },
  915. #endif
  916. { 0, },
  917. };
  918. static int __init pvr2fb_init(void)
  919. {
  920. int i, ret = -ENODEV;
  921. #ifndef MODULE
  922. char *option = NULL;
  923. #endif
  924. if (fb_modesetting_disabled("pvr2fb"))
  925. return -ENODEV;
  926. #ifndef MODULE
  927. if (fb_get_options("pvr2fb", &option))
  928. return -ENODEV;
  929. pvr2fb_setup(option);
  930. #endif
  931. fb_info = framebuffer_alloc(sizeof(struct pvr2fb_par), NULL);
  932. if (!fb_info)
  933. return -ENOMEM;
  934. currentpar = fb_info->par;
  935. for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
  936. struct pvr2_board *pvr_board = board_driver + i;
  937. if (!pvr_board->init)
  938. continue;
  939. ret = pvr_board->init();
  940. if (ret != 0) {
  941. printk(KERN_ERR "pvr2fb: Failed init of %s device\n",
  942. pvr_board->name);
  943. framebuffer_release(fb_info);
  944. break;
  945. }
  946. }
  947. return ret;
  948. }
  949. static void __exit pvr2fb_exit(void)
  950. {
  951. int i;
  952. for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
  953. struct pvr2_board *pvr_board = board_driver + i;
  954. if (pvr_board->exit)
  955. pvr_board->exit();
  956. }
  957. #ifdef CONFIG_SH_STORE_QUEUES
  958. sq_unmap(pvr2fb_map);
  959. #endif
  960. unregister_framebuffer(fb_info);
  961. framebuffer_release(fb_info);
  962. }
  963. module_init(pvr2fb_init);
  964. module_exit(pvr2fb_exit);
  965. MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, M. R. Brown <mrbrown@0xd6.org>");
  966. MODULE_DESCRIPTION("Framebuffer driver for NEC PowerVR 2 based graphics boards");
  967. MODULE_LICENSE("GPL");