1
0

pl320-ipc.c 4.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright 2012 Calxeda, Inc.
  4. */
  5. #include <linux/types.h>
  6. #include <linux/err.h>
  7. #include <linux/delay.h>
  8. #include <linux/export.h>
  9. #include <linux/io.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/completion.h>
  12. #include <linux/mutex.h>
  13. #include <linux/notifier.h>
  14. #include <linux/spinlock.h>
  15. #include <linux/device.h>
  16. #include <linux/amba/bus.h>
  17. #include <linux/pl320-ipc.h>
  18. #define IPCMxSOURCE(m) ((m) * 0x40)
  19. #define IPCMxDSET(m) (((m) * 0x40) + 0x004)
  20. #define IPCMxDCLEAR(m) (((m) * 0x40) + 0x008)
  21. #define IPCMxDSTATUS(m) (((m) * 0x40) + 0x00C)
  22. #define IPCMxMODE(m) (((m) * 0x40) + 0x010)
  23. #define IPCMxMSET(m) (((m) * 0x40) + 0x014)
  24. #define IPCMxMCLEAR(m) (((m) * 0x40) + 0x018)
  25. #define IPCMxMSTATUS(m) (((m) * 0x40) + 0x01C)
  26. #define IPCMxSEND(m) (((m) * 0x40) + 0x020)
  27. #define IPCMxDR(m, dr) (((m) * 0x40) + ((dr) * 4) + 0x024)
  28. #define IPCMMIS(irq) (((irq) * 8) + 0x800)
  29. #define IPCMRIS(irq) (((irq) * 8) + 0x804)
  30. #define MBOX_MASK(n) (1 << (n))
  31. #define IPC_TX_MBOX 1
  32. #define IPC_RX_MBOX 2
  33. #define CHAN_MASK(n) (1 << (n))
  34. #define A9_SOURCE 1
  35. #define M3_SOURCE 0
  36. static void __iomem *ipc_base;
  37. static int ipc_irq;
  38. static DEFINE_MUTEX(ipc_m1_lock);
  39. static DECLARE_COMPLETION(ipc_completion);
  40. static ATOMIC_NOTIFIER_HEAD(ipc_notifier);
  41. static void __ipc_send(int mbox, u32 *data)
  42. {
  43. int i;
  44. for (i = 0; i < 7; i++)
  45. writel_relaxed(data[i], ipc_base + IPCMxDR(mbox, i));
  46. writel_relaxed(0x1, ipc_base + IPCMxSEND(mbox));
  47. }
  48. static u32 __ipc_rcv(int mbox, u32 *data)
  49. {
  50. int i;
  51. for (i = 0; i < 7; i++)
  52. data[i] = readl_relaxed(ipc_base + IPCMxDR(mbox, i));
  53. return data[1];
  54. }
  55. /* blocking implementation from the A9 side, not usable in interrupts! */
  56. int pl320_ipc_transmit(u32 *data)
  57. {
  58. int ret;
  59. mutex_lock(&ipc_m1_lock);
  60. init_completion(&ipc_completion);
  61. __ipc_send(IPC_TX_MBOX, data);
  62. ret = wait_for_completion_timeout(&ipc_completion,
  63. msecs_to_jiffies(1000));
  64. if (ret == 0) {
  65. ret = -ETIMEDOUT;
  66. goto out;
  67. }
  68. ret = __ipc_rcv(IPC_TX_MBOX, data);
  69. out:
  70. mutex_unlock(&ipc_m1_lock);
  71. return ret;
  72. }
  73. EXPORT_SYMBOL_GPL(pl320_ipc_transmit);
  74. static irqreturn_t ipc_handler(int irq, void *dev)
  75. {
  76. u32 irq_stat;
  77. u32 data[7];
  78. irq_stat = readl_relaxed(ipc_base + IPCMMIS(1));
  79. if (irq_stat & MBOX_MASK(IPC_TX_MBOX)) {
  80. writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
  81. complete(&ipc_completion);
  82. }
  83. if (irq_stat & MBOX_MASK(IPC_RX_MBOX)) {
  84. __ipc_rcv(IPC_RX_MBOX, data);
  85. atomic_notifier_call_chain(&ipc_notifier, data[0], data + 1);
  86. writel_relaxed(2, ipc_base + IPCMxSEND(IPC_RX_MBOX));
  87. }
  88. return IRQ_HANDLED;
  89. }
  90. int pl320_ipc_register_notifier(struct notifier_block *nb)
  91. {
  92. return atomic_notifier_chain_register(&ipc_notifier, nb);
  93. }
  94. EXPORT_SYMBOL_GPL(pl320_ipc_register_notifier);
  95. int pl320_ipc_unregister_notifier(struct notifier_block *nb)
  96. {
  97. return atomic_notifier_chain_unregister(&ipc_notifier, nb);
  98. }
  99. EXPORT_SYMBOL_GPL(pl320_ipc_unregister_notifier);
  100. static int pl320_probe(struct amba_device *adev, const struct amba_id *id)
  101. {
  102. int ret;
  103. ipc_base = ioremap(adev->res.start, resource_size(&adev->res));
  104. if (ipc_base == NULL)
  105. return -ENOMEM;
  106. writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
  107. ipc_irq = adev->irq[0];
  108. ret = request_irq(ipc_irq, ipc_handler, 0, dev_name(&adev->dev), NULL);
  109. if (ret < 0)
  110. goto err;
  111. /* Init slow mailbox */
  112. writel_relaxed(CHAN_MASK(A9_SOURCE),
  113. ipc_base + IPCMxSOURCE(IPC_TX_MBOX));
  114. writel_relaxed(CHAN_MASK(M3_SOURCE),
  115. ipc_base + IPCMxDSET(IPC_TX_MBOX));
  116. writel_relaxed(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
  117. ipc_base + IPCMxMSET(IPC_TX_MBOX));
  118. /* Init receive mailbox */
  119. writel_relaxed(CHAN_MASK(M3_SOURCE),
  120. ipc_base + IPCMxSOURCE(IPC_RX_MBOX));
  121. writel_relaxed(CHAN_MASK(A9_SOURCE),
  122. ipc_base + IPCMxDSET(IPC_RX_MBOX));
  123. writel_relaxed(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
  124. ipc_base + IPCMxMSET(IPC_RX_MBOX));
  125. return 0;
  126. err:
  127. iounmap(ipc_base);
  128. return ret;
  129. }
  130. static const struct amba_id pl320_ids[] = {
  131. {
  132. .id = 0x00041320,
  133. .mask = 0x000fffff,
  134. },
  135. { 0, 0 },
  136. };
  137. static struct amba_driver pl320_driver = {
  138. .drv = {
  139. .name = "pl320",
  140. },
  141. .id_table = pl320_ids,
  142. .probe = pl320_probe,
  143. };
  144. static int __init ipc_init(void)
  145. {
  146. return amba_driver_register(&pl320_driver);
  147. }
  148. subsys_initcall(ipc_init);