exynos-mailbox.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright 2020 Samsung Electronics Co., Ltd.
  4. * Copyright 2020 Google LLC.
  5. * Copyright 2024 Linaro Ltd.
  6. */
  7. #include <linux/bitops.h>
  8. #include <linux/bits.h>
  9. #include <linux/clk.h>
  10. #include <linux/io.h>
  11. #include <linux/mailbox_controller.h>
  12. #include <linux/mailbox/exynos-message.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/slab.h>
  17. #define EXYNOS_MBOX_MCUCTRL 0x0 /* Mailbox Control Register */
  18. #define EXYNOS_MBOX_INTCR0 0x24 /* Interrupt Clear Register 0 */
  19. #define EXYNOS_MBOX_INTMR0 0x28 /* Interrupt Mask Register 0 */
  20. #define EXYNOS_MBOX_INTSR0 0x2c /* Interrupt Status Register 0 */
  21. #define EXYNOS_MBOX_INTMSR0 0x30 /* Interrupt Mask Status Register 0 */
  22. #define EXYNOS_MBOX_INTGR1 0x40 /* Interrupt Generation Register 1 */
  23. #define EXYNOS_MBOX_INTMR1 0x48 /* Interrupt Mask Register 1 */
  24. #define EXYNOS_MBOX_INTSR1 0x4c /* Interrupt Status Register 1 */
  25. #define EXYNOS_MBOX_INTMSR1 0x50 /* Interrupt Mask Status Register 1 */
  26. #define EXYNOS_MBOX_INTMR0_MASK GENMASK(15, 0)
  27. #define EXYNOS_MBOX_INTGR1_MASK GENMASK(15, 0)
  28. #define EXYNOS_MBOX_CHAN_COUNT HWEIGHT32(EXYNOS_MBOX_INTGR1_MASK)
  29. /**
  30. * struct exynos_mbox - driver's private data.
  31. * @regs: mailbox registers base address.
  32. * @mbox: pointer to the mailbox controller.
  33. */
  34. struct exynos_mbox {
  35. void __iomem *regs;
  36. struct mbox_controller *mbox;
  37. };
  38. static int exynos_mbox_send_data(struct mbox_chan *chan, void *data)
  39. {
  40. struct device *dev = chan->mbox->dev;
  41. struct exynos_mbox *exynos_mbox = dev_get_drvdata(dev);
  42. struct exynos_mbox_msg *msg = data;
  43. if (msg->chan_id >= exynos_mbox->mbox->num_chans) {
  44. dev_err(dev, "Invalid channel ID %d\n", msg->chan_id);
  45. return -EINVAL;
  46. }
  47. if (msg->chan_type != EXYNOS_MBOX_CHAN_TYPE_DOORBELL) {
  48. dev_err(dev, "Unsupported channel type [%d]\n", msg->chan_type);
  49. return -EINVAL;
  50. }
  51. writel(BIT(msg->chan_id), exynos_mbox->regs + EXYNOS_MBOX_INTGR1);
  52. return 0;
  53. }
  54. static const struct mbox_chan_ops exynos_mbox_chan_ops = {
  55. .send_data = exynos_mbox_send_data,
  56. };
  57. static struct mbox_chan *exynos_mbox_of_xlate(struct mbox_controller *mbox,
  58. const struct of_phandle_args *sp)
  59. {
  60. int i;
  61. if (sp->args_count != 0)
  62. return ERR_PTR(-EINVAL);
  63. /*
  64. * Return the first available channel. When we don't pass the
  65. * channel ID from device tree, each channel populated by the driver is
  66. * just a software construct or a virtual channel. We use 'void *data'
  67. * in send_data() to pass the channel identifiers.
  68. */
  69. for (i = 0; i < mbox->num_chans; i++)
  70. if (mbox->chans[i].cl == NULL)
  71. return &mbox->chans[i];
  72. return ERR_PTR(-EINVAL);
  73. }
  74. static const struct of_device_id exynos_mbox_match[] = {
  75. { .compatible = "google,gs101-mbox" },
  76. {},
  77. };
  78. MODULE_DEVICE_TABLE(of, exynos_mbox_match);
  79. static int exynos_mbox_probe(struct platform_device *pdev)
  80. {
  81. struct device *dev = &pdev->dev;
  82. struct exynos_mbox *exynos_mbox;
  83. struct mbox_controller *mbox;
  84. struct mbox_chan *chans;
  85. struct clk *pclk;
  86. int i;
  87. exynos_mbox = devm_kzalloc(dev, sizeof(*exynos_mbox), GFP_KERNEL);
  88. if (!exynos_mbox)
  89. return -ENOMEM;
  90. mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
  91. if (!mbox)
  92. return -ENOMEM;
  93. chans = devm_kcalloc(dev, EXYNOS_MBOX_CHAN_COUNT, sizeof(*chans),
  94. GFP_KERNEL);
  95. if (!chans)
  96. return -ENOMEM;
  97. exynos_mbox->regs = devm_platform_ioremap_resource(pdev, 0);
  98. if (IS_ERR(exynos_mbox->regs))
  99. return PTR_ERR(exynos_mbox->regs);
  100. pclk = devm_clk_get_enabled(dev, "pclk");
  101. if (IS_ERR(pclk))
  102. return dev_err_probe(dev, PTR_ERR(pclk),
  103. "Failed to enable clock.\n");
  104. mbox->num_chans = EXYNOS_MBOX_CHAN_COUNT;
  105. mbox->chans = chans;
  106. mbox->dev = dev;
  107. mbox->ops = &exynos_mbox_chan_ops;
  108. mbox->of_xlate = exynos_mbox_of_xlate;
  109. for (i = 0; i < EXYNOS_MBOX_CHAN_COUNT; i++)
  110. chans[i].mbox = mbox;
  111. exynos_mbox->mbox = mbox;
  112. platform_set_drvdata(pdev, exynos_mbox);
  113. /* Mask out all interrupts. We support just polling channels for now. */
  114. writel(EXYNOS_MBOX_INTMR0_MASK, exynos_mbox->regs + EXYNOS_MBOX_INTMR0);
  115. return devm_mbox_controller_register(dev, mbox);
  116. }
  117. static struct platform_driver exynos_mbox_driver = {
  118. .probe = exynos_mbox_probe,
  119. .driver = {
  120. .name = "exynos-acpm-mbox",
  121. .of_match_table = exynos_mbox_match,
  122. },
  123. };
  124. module_platform_driver(exynos_mbox_driver);
  125. MODULE_AUTHOR("Tudor Ambarus <tudor.ambarus@linaro.org>");
  126. MODULE_DESCRIPTION("Samsung Exynos mailbox driver");
  127. MODULE_LICENSE("GPL");