Kconfig 14 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. menuconfig MAILBOX
  3. bool "Mailbox Hardware Support"
  4. help
  5. Mailbox is a framework to control hardware communication between
  6. on-chip processors through queued messages and interrupt driven
  7. signals. Say Y if your platform supports hardware mailboxes.
  8. if MAILBOX
  9. config ARM_MHU
  10. tristate "ARM MHU Mailbox"
  11. depends on ARM_AMBA
  12. help
  13. Say Y here if you want to build the ARM MHU controller driver.
  14. The controller has 3 mailbox channels, the last of which can be
  15. used in Secure mode only.
  16. config ARM_MHU_V2
  17. tristate "ARM MHUv2 Mailbox"
  18. depends on ARM_AMBA
  19. help
  20. Say Y here if you want to build the ARM MHUv2 controller driver,
  21. which provides unidirectional mailboxes between processing elements.
  22. config ARM_MHU_V3
  23. tristate "ARM MHUv3 Mailbox"
  24. depends on ARM64 || COMPILE_TEST
  25. depends on HAS_IOMEM || COMPILE_TEST
  26. depends on OF
  27. help
  28. Say Y here if you want to build the ARM MHUv3 controller driver,
  29. which provides unidirectional mailboxes between processing elements.
  30. ARM MHUv3 controllers can implement a varying number of extensions
  31. that provides different means of transports: supported extensions
  32. will be discovered and possibly managed at probe-time.
  33. config AST2700_MBOX
  34. tristate "ASPEED AST2700 IPC driver"
  35. depends on ARCH_ASPEED || COMPILE_TEST
  36. help
  37. Mailbox driver implementation for ASPEED AST27XX SoCs. This driver
  38. can be used to send message between different processors in SoC.
  39. The driver provides mailbox support for sending interrupts to the
  40. clients. Say Y here if you want to build this driver.
  41. config CV1800_MBOX
  42. tristate "cv1800 mailbox"
  43. depends on ARCH_SOPHGO || COMPILE_TEST
  44. help
  45. Mailbox driver implementation for Sophgo CV18XX SoCs. This driver
  46. can be used to send message between different processors in SoC. Any
  47. processer can write data in a channel, and set co-responding register
  48. to raise interrupt to notice another processor, and it is allowed to
  49. send data to itself.
  50. config EXYNOS_MBOX
  51. tristate "Exynos Mailbox"
  52. depends on ARCH_EXYNOS || COMPILE_TEST
  53. help
  54. Say Y here if you want to build the Samsung Exynos Mailbox controller
  55. driver. The controller has 16 flag bits for hardware interrupt
  56. generation and a shared register for passing mailbox messages.
  57. When the controller is used by the ACPM interface the shared register
  58. is ignored and the mailbox controller acts as a doorbell that raises
  59. the interrupt to the ACPM firmware.
  60. config IMX_MBOX
  61. tristate "i.MX Mailbox"
  62. depends on ARCH_MXC || COMPILE_TEST
  63. help
  64. Mailbox implementation for i.MX Messaging Unit (MU).
  65. config PLATFORM_MHU
  66. tristate "Platform MHU Mailbox"
  67. depends on OF
  68. depends on HAS_IOMEM
  69. help
  70. Say Y here if you want to build a platform specific variant MHU
  71. controller driver.
  72. The controller has a maximum of 3 mailbox channels, the last of
  73. which can be used in Secure mode only.
  74. config PL320_MBOX
  75. bool "ARM PL320 Mailbox"
  76. depends on ARM_AMBA
  77. help
  78. An implementation of the ARM PL320 Interprocessor Communication
  79. Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to
  80. send short messages between Highbank's A9 cores and the EnergyCore
  81. Management Engine, primarily for cpufreq. Say Y here if you want
  82. to use the PL320 IPCM support.
  83. config ARMADA_37XX_RWTM_MBOX
  84. tristate "Armada 37xx rWTM BIU Mailbox"
  85. depends on ARCH_MVEBU || COMPILE_TEST
  86. depends on OF
  87. help
  88. Mailbox implementation for communication with the the firmware
  89. running on the Cortex-M3 rWTM secure processor of the Armada 37xx
  90. SOC. Say Y here if you are building for such a device (for example
  91. the Turris Mox router).
  92. config OMAP2PLUS_MBOX
  93. tristate "OMAP2+ Mailbox framework support"
  94. depends on ARCH_OMAP2PLUS || ARCH_K3 || COMPILE_TEST
  95. help
  96. Mailbox implementation for OMAP family chips with hardware for
  97. interprocessor communication involving DSP, IVA1.0 and IVA2 in
  98. OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you
  99. want to use OMAP2+ Mailbox framework support.
  100. config ROCKCHIP_MBOX
  101. bool "Rockchip Soc Integrated Mailbox Support"
  102. depends on ARCH_ROCKCHIP || COMPILE_TEST
  103. help
  104. This driver provides support for inter-processor communication
  105. between CPU cores and MCU processor on Some Rockchip SOCs.
  106. Please check it that the Soc you use have Mailbox hardware.
  107. Say Y here if you want to use the Rockchip Mailbox support.
  108. config PCC
  109. bool "Platform Communication Channel Driver"
  110. depends on ACPI
  111. default n
  112. help
  113. ACPI 5.0+ spec defines a generic mode of communication
  114. between the OS and a platform such as the BMC. This medium
  115. (PCC) is typically used by CPPC (ACPI CPU Performance management),
  116. RAS (ACPI reliability protocol) and MPST (ACPI Memory power
  117. states). Select this driver if your platform implements the
  118. PCC clients mentioned above.
  119. config ALTERA_MBOX
  120. tristate "Altera Mailbox"
  121. depends on HAS_IOMEM
  122. help
  123. An implementation of the Altera Mailbox soft core. It is used
  124. to send message between processors. Say Y here if you want to use the
  125. Altera mailbox support.
  126. config BCM2835_MBOX
  127. tristate "BCM2835 Mailbox"
  128. depends on ARCH_BCM2835
  129. help
  130. An implementation of the BCM2385 Mailbox. It is used to invoke
  131. the services of the Videocore. Say Y here if you want to use the
  132. BCM2835 Mailbox.
  133. config STI_MBOX
  134. tristate "STI Mailbox framework support"
  135. depends on ARCH_STI && OF
  136. help
  137. Mailbox implementation for STMicroelectonics family chips with
  138. hardware for interprocessor communication.
  139. config TI_MESSAGE_MANAGER
  140. tristate "Texas Instruments Message Manager Driver"
  141. depends on ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST
  142. default ARCH_K3
  143. help
  144. An implementation of Message Manager slave driver for Keystone
  145. and K3 architecture SoCs from Texas Instruments. Message Manager
  146. is a communication entity found on few of Texas Instrument's keystone
  147. and K3 architecture SoCs. These may be used for communication between
  148. multiple processors within the SoC. Select this driver if your
  149. platform has support for the hardware block.
  150. config HI3660_MBOX
  151. tristate "Hi3660 Mailbox" if EXPERT
  152. depends on (ARCH_HISI || COMPILE_TEST)
  153. depends on OF
  154. default ARCH_HISI
  155. help
  156. An implementation of the hi3660 mailbox. It is used to send message
  157. between application processors and other processors/MCU/DSP. Select
  158. Y here if you want to use Hi3660 mailbox controller.
  159. config HI6220_MBOX
  160. tristate "Hi6220 Mailbox" if EXPERT
  161. depends on (ARCH_HISI || COMPILE_TEST)
  162. depends on OF
  163. default ARCH_HISI
  164. help
  165. An implementation of the hi6220 mailbox. It is used to send message
  166. between application processors and MCU. Say Y here if you want to
  167. build Hi6220 mailbox controller driver.
  168. config MAILBOX_TEST
  169. tristate "Mailbox Test Client"
  170. depends on OF
  171. depends on HAS_IOMEM
  172. help
  173. Test client to help with testing new Controller driver
  174. implementations.
  175. config POLARFIRE_SOC_MAILBOX
  176. tristate "PolarFire SoC (MPFS) Mailbox"
  177. depends on HAS_IOMEM
  178. depends on MFD_SYSCON
  179. depends on ARCH_MICROCHIP || COMPILE_TEST
  180. help
  181. This driver adds support for the PolarFire SoC (MPFS) mailbox controller.
  182. To compile this driver as a module, choose M here. the
  183. module will be called mailbox-mpfs.
  184. If unsure, say N.
  185. config MCHP_SBI_IPC_MBOX
  186. tristate "Microchip Inter-processor Communication (IPC) SBI driver"
  187. depends on RISCV_SBI
  188. depends on ARCH_MICROCHIP || COMPILE_TEST
  189. help
  190. Mailbox implementation for Microchip devices with an
  191. Inter-process communication (IPC) controller.
  192. To compile this driver as a module, choose M here. the
  193. module will be called mailbox-mchp-ipc-sbi.
  194. If unsure, say N.
  195. config QCOM_APCS_IPC
  196. tristate "Qualcomm APCS IPC driver"
  197. depends on ARCH_QCOM || COMPILE_TEST
  198. help
  199. Say y here to enable support for the APCS IPC mailbox driver,
  200. providing an interface for invoking the inter-process communication
  201. signals from the application processor to other masters.
  202. config TEGRA_HSP_MBOX
  203. bool "Tegra HSP (Hardware Synchronization Primitives) Driver"
  204. depends on ARCH_TEGRA
  205. help
  206. The Tegra HSP driver is used for the interprocessor communication
  207. between different remote processors and host processors on Tegra186
  208. and later SoCs. Say Y here if you want to have this support.
  209. If unsure say N.
  210. config XGENE_SLIMPRO_MBOX
  211. tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
  212. depends on ARCH_XGENE
  213. help
  214. An implementation of the APM X-Gene Interprocessor Communication
  215. Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
  216. It is used to send short messages between ARM64-bit cores and
  217. the SLIMpro Management Engine, primarily for PM. Say Y here if you
  218. want to use the APM X-Gene SLIMpro IPCM support.
  219. config BCM_PDC_MBOX
  220. tristate "Broadcom FlexSparx DMA Mailbox"
  221. depends on ARCH_BCM_IPROC || COMPILE_TEST
  222. help
  223. Mailbox implementation for the Broadcom FlexSparx DMA ring manager,
  224. which provides access to various offload engines on Broadcom
  225. SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2.
  226. config BCM_FLEXRM_MBOX
  227. tristate "Broadcom FlexRM Mailbox"
  228. depends on ARM64
  229. depends on ARCH_BCM_IPROC || COMPILE_TEST
  230. select GENERIC_MSI_IRQ
  231. default m if ARCH_BCM_IPROC
  232. help
  233. Mailbox implementation of the Broadcom FlexRM ring manager,
  234. which provides access to various offload engines on Broadcom
  235. SoCs. Say Y here if you want to use the Broadcom FlexRM.
  236. config STM32_IPCC
  237. tristate "STM32 IPCC Mailbox"
  238. depends on MACH_STM32MP157 || COMPILE_TEST
  239. help
  240. Mailbox implementation for STMicroelectonics STM32 family chips
  241. with hardware for Inter-Processor Communication Controller (IPCC)
  242. between processors. Say Y here if you want to have this support.
  243. config MTK_ADSP_MBOX
  244. tristate "MediaTek ADSP Mailbox Controller"
  245. depends on ARCH_MEDIATEK || COMPILE_TEST
  246. help
  247. Say yes here to add support for MediaTek ADSP Mailbox Controller.
  248. This mailbox driver is used to send notification or short message
  249. between processors with ADSP. It will place the message to share
  250. buffer and will access the ipc control.
  251. config MTK_CMDQ_MBOX
  252. tristate "MediaTek CMDQ Mailbox Support"
  253. depends on ARCH_MEDIATEK || COMPILE_TEST
  254. select MTK_INFRACFG
  255. help
  256. Say yes here to add support for the MediaTek Command Queue (CMDQ)
  257. mailbox driver. The CMDQ is used to help read/write registers with
  258. critical time limitation, such as updating display configuration
  259. during the vblank.
  260. config MTK_GPUEB_MBOX
  261. tristate "MediaTek GPUEB Mailbox Support"
  262. depends on ARCH_MEDIATEK || COMPILE_TEST
  263. help
  264. The MediaTek GPUEB mailbox is used to communicate with the embedded
  265. controller in charge of GPU frequency and power management on some
  266. MediaTek SoCs, such as the MT8196.
  267. Say Y or m here if you want to support the MT8196 SoC in your kernel
  268. build.
  269. config MTK_VCP_MBOX
  270. tristate "MediaTek VCP Mailbox Support"
  271. depends on ARCH_MEDIATEK || COMPILE_TEST
  272. help
  273. Say yes here to add support for the MediaTek VCP mailbox driver.
  274. The mailbox implementation provides access from the application
  275. processor to Video Companion Processor Unit.
  276. If unsure say N.
  277. config ZYNQMP_IPI_MBOX
  278. tristate "Xilinx ZynqMP IPI Mailbox"
  279. depends on ARCH_ZYNQMP && OF
  280. help
  281. Say yes here to add support for Xilinx IPI mailbox driver.
  282. This mailbox driver is used to send notification or short message
  283. between processors with Xilinx ZynqMP IPI. It will place the
  284. message to the IPI buffer and will access the IPI control
  285. registers to kick the other processor or enquire status.
  286. config SUN6I_MSGBOX
  287. tristate "Allwinner sun6i/sun8i/sun9i/sun50i Message Box"
  288. depends on ARCH_SUNXI || COMPILE_TEST
  289. default ARCH_SUNXI
  290. help
  291. Mailbox implementation for the hardware message box present in
  292. various Allwinner SoCs. This mailbox is used for communication
  293. between the application CPUs and the power management coprocessor.
  294. config SPRD_MBOX
  295. tristate "Spreadtrum Mailbox"
  296. depends on ARCH_SPRD || COMPILE_TEST
  297. help
  298. Mailbox driver implementation for the Spreadtrum platform. It is used
  299. to send message between application processors and MCU. Say Y here if
  300. you want to build the Spreatrum mailbox controller driver.
  301. config QCOM_CPUCP_MBOX
  302. tristate "Qualcomm Technologies, Inc. CPUCP mailbox driver"
  303. depends on (ARCH_QCOM || COMPILE_TEST) && 64BIT
  304. help
  305. Qualcomm Technologies, Inc. CPUSS Control Processor (CPUCP) mailbox
  306. controller driver enables communication between AP and CPUCP. Say
  307. Y here if you want to build this driver.
  308. config QCOM_IPCC
  309. tristate "Qualcomm Technologies, Inc. IPCC driver"
  310. depends on ARCH_QCOM || COMPILE_TEST
  311. help
  312. Qualcomm Technologies, Inc. Inter-Processor Communication Controller
  313. (IPCC) driver for MSM devices. The driver provides mailbox support for
  314. sending interrupts to the clients. On the other hand, the driver also
  315. acts as an interrupt controller for receiving interrupts from clients.
  316. Say Y here if you want to build this driver.
  317. config THEAD_TH1520_MBOX
  318. tristate "T-head TH1520 Mailbox"
  319. depends on ARCH_THEAD || COMPILE_TEST
  320. help
  321. Mailbox driver implementation for the Thead TH-1520 platform. Enables
  322. two cores within the SoC to communicate and coordinate by passing
  323. messages. Could be used to communicate between E910 core, on which the
  324. kernel is running, and E902 core used for power management among other
  325. things.
  326. config CIX_MBOX
  327. tristate "CIX Mailbox"
  328. depends on ARCH_CIX || COMPILE_TEST
  329. depends on OF
  330. help
  331. Mailbox implementation for CIX IPC system. The controller supports
  332. 11 mailbox channels with different operating mode and every channel
  333. is unidirectional. Say Y here if you want to use the CIX Mailbox
  334. support.
  335. config BCM74110_MAILBOX
  336. tristate "Brcmstb BCM74110 Mailbox"
  337. depends on ARCH_BRCMSTB || COMPILE_TEST
  338. default ARCH_BRCMSTB
  339. help
  340. Broadcom STB mailbox driver present starting with brcmstb bcm74110
  341. SoCs. The mailbox is a communication channel between the host
  342. processor and coprocessor that handles various power management task
  343. and more.
  344. config RISCV_SBI_MPXY_MBOX
  345. tristate "RISC-V SBI Message Proxy (MPXY) Mailbox"
  346. depends on RISCV_SBI
  347. default RISCV
  348. help
  349. Mailbox driver implementation for RISC-V SBI Message Proxy (MPXY)
  350. extension. This mailbox driver is used to send messages to the
  351. remote processor through the SBI implementation (M-mode firmware
  352. or HS-mode hypervisor). Say Y here, unless you are sure you do not
  353. need this.
  354. endif