pvr_device.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only OR MIT
  2. /* Copyright (c) 2023 Imagination Technologies Ltd. */
  3. #include "pvr_device.h"
  4. #include "pvr_device_info.h"
  5. #include "pvr_fw.h"
  6. #include "pvr_power.h"
  7. #include "pvr_queue.h"
  8. #include "pvr_rogue_cr_defs.h"
  9. #include "pvr_stream.h"
  10. #include "pvr_vm.h"
  11. #include <drm/drm_print.h>
  12. #include <linux/bitfield.h>
  13. #include <linux/clk.h>
  14. #include <linux/compiler_attributes.h>
  15. #include <linux/compiler_types.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/err.h>
  18. #include <linux/firmware.h>
  19. #include <linux/gfp.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/of.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/pm_runtime.h>
  24. #include <linux/reset.h>
  25. #include <linux/slab.h>
  26. #include <linux/stddef.h>
  27. #include <linux/types.h>
  28. #include <linux/workqueue.h>
  29. #include <kunit/visibility.h>
  30. /* Major number for the supported version of the firmware. */
  31. #define PVR_FW_VERSION_MAJOR 1
  32. /**
  33. * pvr_device_reg_init() - Initialize kernel access to a PowerVR device's
  34. * control registers.
  35. * @pvr_dev: Target PowerVR device.
  36. *
  37. * Sets struct pvr_device->regs.
  38. *
  39. * This method of mapping the device control registers into memory ensures that
  40. * they are unmapped when the driver is detached (i.e. no explicit cleanup is
  41. * required).
  42. *
  43. * Return:
  44. * * 0 on success, or
  45. * * Any error returned by devm_platform_get_and_ioremap_resource().
  46. */
  47. static int
  48. pvr_device_reg_init(struct pvr_device *pvr_dev)
  49. {
  50. struct drm_device *drm_dev = from_pvr_device(pvr_dev);
  51. struct platform_device *plat_dev = to_platform_device(drm_dev->dev);
  52. struct resource *regs_resource;
  53. void __iomem *regs;
  54. pvr_dev->regs_resource = NULL;
  55. pvr_dev->regs = NULL;
  56. regs = devm_platform_get_and_ioremap_resource(plat_dev, 0, &regs_resource);
  57. if (IS_ERR(regs))
  58. return dev_err_probe(drm_dev->dev, PTR_ERR(regs),
  59. "failed to ioremap gpu registers\n");
  60. pvr_dev->regs = regs;
  61. pvr_dev->regs_resource = regs_resource;
  62. return 0;
  63. }
  64. /**
  65. * pvr_device_clk_init() - Initialize clocks required by a PowerVR device
  66. * @pvr_dev: Target PowerVR device.
  67. *
  68. * Sets struct pvr_device->core_clk, struct pvr_device->sys_clk and
  69. * struct pvr_device->mem_clk.
  70. *
  71. * Three clocks are required by the PowerVR device: core, sys and mem. On
  72. * return, this function guarantees that the clocks are in one of the following
  73. * states:
  74. *
  75. * * All successfully initialized,
  76. * * Core errored, sys and mem uninitialized,
  77. * * Core deinitialized, sys errored, mem uninitialized, or
  78. * * Core and sys deinitialized, mem errored.
  79. *
  80. * Return:
  81. * * 0 on success,
  82. * * Any error returned by devm_clk_get(), or
  83. * * Any error returned by devm_clk_get_optional().
  84. */
  85. static int pvr_device_clk_init(struct pvr_device *pvr_dev)
  86. {
  87. struct drm_device *drm_dev = from_pvr_device(pvr_dev);
  88. struct clk *core_clk;
  89. struct clk *sys_clk;
  90. struct clk *mem_clk;
  91. core_clk = devm_clk_get(drm_dev->dev, "core");
  92. if (IS_ERR(core_clk))
  93. return dev_err_probe(drm_dev->dev, PTR_ERR(core_clk),
  94. "failed to get core clock\n");
  95. sys_clk = devm_clk_get_optional(drm_dev->dev, "sys");
  96. if (IS_ERR(sys_clk))
  97. return dev_err_probe(drm_dev->dev, PTR_ERR(sys_clk),
  98. "failed to get sys clock\n");
  99. mem_clk = devm_clk_get_optional(drm_dev->dev, "mem");
  100. if (IS_ERR(mem_clk))
  101. return dev_err_probe(drm_dev->dev, PTR_ERR(mem_clk),
  102. "failed to get mem clock\n");
  103. pvr_dev->core_clk = core_clk;
  104. pvr_dev->sys_clk = sys_clk;
  105. pvr_dev->mem_clk = mem_clk;
  106. return 0;
  107. }
  108. /**
  109. * pvr_device_process_active_queues() - Process all queue related events.
  110. * @pvr_dev: PowerVR device to check
  111. *
  112. * This is called any time we receive a FW event. It iterates over all
  113. * active queues and calls pvr_queue_process() on them.
  114. */
  115. static void pvr_device_process_active_queues(struct pvr_device *pvr_dev)
  116. {
  117. struct pvr_queue *queue, *tmp_queue;
  118. LIST_HEAD(active_queues);
  119. mutex_lock(&pvr_dev->queues.lock);
  120. /* Move all active queues to a temporary list. Queues that remain
  121. * active after we're done processing them are re-inserted to
  122. * the queues.active list by pvr_queue_process().
  123. */
  124. list_splice_init(&pvr_dev->queues.active, &active_queues);
  125. list_for_each_entry_safe(queue, tmp_queue, &active_queues, node)
  126. pvr_queue_process(queue);
  127. mutex_unlock(&pvr_dev->queues.lock);
  128. }
  129. static bool pvr_device_safety_irq_pending(struct pvr_device *pvr_dev)
  130. {
  131. u32 events;
  132. WARN_ON_ONCE(!pvr_dev->has_safety_events);
  133. events = pvr_cr_read32(pvr_dev, ROGUE_CR_EVENT_STATUS);
  134. return (events & ROGUE_CR_EVENT_STATUS_SAFETY_EN) != 0;
  135. }
  136. static void pvr_device_safety_irq_clear(struct pvr_device *pvr_dev)
  137. {
  138. WARN_ON_ONCE(!pvr_dev->has_safety_events);
  139. pvr_cr_write32(pvr_dev, ROGUE_CR_EVENT_CLEAR,
  140. ROGUE_CR_EVENT_CLEAR_SAFETY_EN);
  141. }
  142. static void pvr_device_handle_safety_events(struct pvr_device *pvr_dev)
  143. {
  144. struct drm_device *drm_dev = from_pvr_device(pvr_dev);
  145. u32 events;
  146. WARN_ON_ONCE(!pvr_dev->has_safety_events);
  147. events = pvr_cr_read32(pvr_dev, ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE);
  148. /* Handle only these events on the host and leave the rest to the FW. */
  149. events &= ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_FW_EN |
  150. ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__WATCHDOG_TIMEOUT_EN;
  151. pvr_cr_write32(pvr_dev, ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE, events);
  152. if (events & ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_FW_EN) {
  153. u32 fault_fw = pvr_cr_read32(pvr_dev, ROGUE_CR_FAULT_FW_STATUS);
  154. pvr_cr_write32(pvr_dev, ROGUE_CR_FAULT_FW_CLEAR, fault_fw);
  155. drm_info(drm_dev, "Safety event: FW fault (mask=0x%08x)\n", fault_fw);
  156. }
  157. if (events & ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__WATCHDOG_TIMEOUT_EN) {
  158. /*
  159. * The watchdog timer is disabled by the driver so this event
  160. * should never be fired.
  161. */
  162. drm_info(drm_dev, "Safety event: Watchdog timeout\n");
  163. }
  164. }
  165. static irqreturn_t pvr_device_irq_thread_handler(int irq, void *data)
  166. {
  167. struct pvr_device *pvr_dev = data;
  168. struct drm_device *drm_dev = from_pvr_device(pvr_dev);
  169. irqreturn_t ret = IRQ_NONE;
  170. /* We are in the threaded handler, we can keep dequeuing events until we
  171. * don't see any. This should allow us to reduce the number of interrupts
  172. * when the GPU is receiving a massive amount of short jobs.
  173. */
  174. while (pvr_fw_irq_pending(pvr_dev)) {
  175. pvr_fw_irq_clear(pvr_dev);
  176. if (pvr_dev->fw_dev.booted) {
  177. pvr_fwccb_process(pvr_dev);
  178. pvr_kccb_wake_up_waiters(pvr_dev);
  179. pvr_device_process_active_queues(pvr_dev);
  180. }
  181. pm_runtime_mark_last_busy(drm_dev->dev);
  182. ret = IRQ_HANDLED;
  183. }
  184. if (pvr_dev->has_safety_events) {
  185. while (pvr_device_safety_irq_pending(pvr_dev)) {
  186. pvr_device_safety_irq_clear(pvr_dev);
  187. pvr_device_handle_safety_events(pvr_dev);
  188. ret = IRQ_HANDLED;
  189. }
  190. }
  191. return ret;
  192. }
  193. static irqreturn_t pvr_device_irq_handler(int irq, void *data)
  194. {
  195. struct pvr_device *pvr_dev = data;
  196. bool safety_irq_pending = false;
  197. if (pvr_dev->has_safety_events)
  198. safety_irq_pending = pvr_device_safety_irq_pending(pvr_dev);
  199. if (!pvr_fw_irq_pending(pvr_dev) && !safety_irq_pending)
  200. return IRQ_NONE; /* Spurious IRQ - ignore. */
  201. return IRQ_WAKE_THREAD;
  202. }
  203. static void pvr_device_safety_irq_init(struct pvr_device *pvr_dev)
  204. {
  205. u32 num_ecc_rams = 0;
  206. /*
  207. * Safety events are an optional feature of the RogueXE platform. They
  208. * are only enabled if at least one of ECC memory or the watchdog timer
  209. * are present in HW. While safety events can be generated by other
  210. * systems, that will never happen if the above mentioned hardware is
  211. * not present.
  212. */
  213. if (!PVR_HAS_FEATURE(pvr_dev, roguexe)) {
  214. pvr_dev->has_safety_events = false;
  215. return;
  216. }
  217. PVR_FEATURE_VALUE(pvr_dev, ecc_rams, &num_ecc_rams);
  218. pvr_dev->has_safety_events =
  219. num_ecc_rams > 0 || PVR_HAS_FEATURE(pvr_dev, watchdog_timer);
  220. }
  221. /**
  222. * pvr_device_irq_init() - Initialise IRQ required by a PowerVR device
  223. * @pvr_dev: Target PowerVR device.
  224. *
  225. * Returns:
  226. * * 0 on success,
  227. * * Any error returned by platform_get_irq_byname(), or
  228. * * Any error returned by request_irq().
  229. */
  230. static int
  231. pvr_device_irq_init(struct pvr_device *pvr_dev)
  232. {
  233. struct drm_device *drm_dev = from_pvr_device(pvr_dev);
  234. struct platform_device *plat_dev = to_platform_device(drm_dev->dev);
  235. init_waitqueue_head(&pvr_dev->kccb.rtn_q);
  236. pvr_device_safety_irq_init(pvr_dev);
  237. pvr_dev->irq = platform_get_irq(plat_dev, 0);
  238. if (pvr_dev->irq < 0)
  239. return pvr_dev->irq;
  240. /* Clear any pending events before requesting the IRQ line. */
  241. pvr_fw_irq_clear(pvr_dev);
  242. if (pvr_dev->has_safety_events)
  243. pvr_device_safety_irq_clear(pvr_dev);
  244. /*
  245. * The ONESHOT flag ensures IRQs are masked while the thread handler is
  246. * running.
  247. */
  248. return request_threaded_irq(pvr_dev->irq, pvr_device_irq_handler,
  249. pvr_device_irq_thread_handler,
  250. IRQF_SHARED | IRQF_ONESHOT, "gpu", pvr_dev);
  251. }
  252. /**
  253. * pvr_device_irq_fini() - Deinitialise IRQ required by a PowerVR device
  254. * @pvr_dev: Target PowerVR device.
  255. */
  256. static void
  257. pvr_device_irq_fini(struct pvr_device *pvr_dev)
  258. {
  259. free_irq(pvr_dev->irq, pvr_dev);
  260. }
  261. /**
  262. * pvr_build_firmware_filename() - Construct a PowerVR firmware filename
  263. * @pvr_dev: Target PowerVR device.
  264. * @base: First part of the filename.
  265. * @major: Major version number.
  266. *
  267. * A PowerVR firmware filename consists of three parts separated by underscores
  268. * (``'_'``) along with a '.fw' file suffix. The first part is the exact value
  269. * of @base, the second part is the hardware version string derived from @pvr_fw
  270. * and the final part is the firmware version number constructed from @major with
  271. * a 'v' prefix, e.g. powervr/rogue_4.40.2.51_v1.fw.
  272. *
  273. * The returned string will have been slab allocated and must be freed with
  274. * kfree().
  275. *
  276. * Return:
  277. * * The constructed filename on success, or
  278. * * Any error returned by kasprintf().
  279. */
  280. static char *
  281. pvr_build_firmware_filename(struct pvr_device *pvr_dev, const char *base,
  282. u8 major)
  283. {
  284. struct pvr_gpu_id *gpu_id = &pvr_dev->gpu_id;
  285. return kasprintf(GFP_KERNEL, "%s_%d.%d.%d.%d_v%d.fw", base, gpu_id->b,
  286. gpu_id->v, gpu_id->n, gpu_id->c, major);
  287. }
  288. static void
  289. pvr_release_firmware(void *data)
  290. {
  291. struct pvr_device *pvr_dev = data;
  292. release_firmware(pvr_dev->fw_dev.firmware);
  293. }
  294. /**
  295. * pvr_request_firmware() - Load firmware for a PowerVR device
  296. * @pvr_dev: Target PowerVR device.
  297. *
  298. * See pvr_build_firmware_filename() for details on firmware file naming.
  299. *
  300. * Return:
  301. * * 0 on success,
  302. * * Any error returned by pvr_build_firmware_filename(), or
  303. * * Any error returned by request_firmware().
  304. */
  305. static int
  306. pvr_request_firmware(struct pvr_device *pvr_dev)
  307. {
  308. struct drm_device *drm_dev = &pvr_dev->base;
  309. char *filename;
  310. const struct firmware *fw;
  311. int err;
  312. filename = pvr_build_firmware_filename(pvr_dev, "powervr/rogue",
  313. PVR_FW_VERSION_MAJOR);
  314. if (!filename)
  315. return -ENOMEM;
  316. /*
  317. * This function takes a copy of &filename, meaning we can free our
  318. * instance before returning.
  319. */
  320. err = request_firmware(&fw, filename, pvr_dev->base.dev);
  321. if (err) {
  322. drm_err(drm_dev, "failed to load firmware %s (err=%d)\n",
  323. filename, err);
  324. goto err_free_filename;
  325. }
  326. drm_info(drm_dev, "loaded firmware %s\n", filename);
  327. kfree(filename);
  328. pvr_dev->fw_dev.firmware = fw;
  329. return devm_add_action_or_reset(drm_dev->dev, pvr_release_firmware, pvr_dev);
  330. err_free_filename:
  331. kfree(filename);
  332. return err;
  333. }
  334. /**
  335. * pvr_gpuid_decode_reg() - Decode the GPU ID from GPU register
  336. *
  337. * Sets the b, v, n, c fields of struct pvr_dev.gpu_id.
  338. *
  339. * @pvr_dev: Target PowerVR device.
  340. * @gpu_id: Output to be updated with the GPU ID.
  341. */
  342. static void
  343. pvr_gpuid_decode_reg(const struct pvr_device *pvr_dev, struct pvr_gpu_id *gpu_id)
  344. {
  345. /*
  346. * Try reading the BVNC using the newer (cleaner) method first. If the
  347. * B value is zero, fall back to the older method.
  348. */
  349. u64 bvnc = pvr_cr_read64(pvr_dev, ROGUE_CR_CORE_ID__PBVNC);
  350. gpu_id->b = PVR_CR_FIELD_GET(bvnc, CORE_ID__PBVNC__BRANCH_ID);
  351. if (gpu_id->b != 0) {
  352. gpu_id->v = PVR_CR_FIELD_GET(bvnc, CORE_ID__PBVNC__VERSION_ID);
  353. gpu_id->n = PVR_CR_FIELD_GET(bvnc, CORE_ID__PBVNC__NUMBER_OF_SCALABLE_UNITS);
  354. gpu_id->c = PVR_CR_FIELD_GET(bvnc, CORE_ID__PBVNC__CONFIG_ID);
  355. } else {
  356. u32 core_rev = pvr_cr_read32(pvr_dev, ROGUE_CR_CORE_REVISION);
  357. u32 core_id = pvr_cr_read32(pvr_dev, ROGUE_CR_CORE_ID);
  358. u16 core_id_config = PVR_CR_FIELD_GET(core_id, CORE_ID_CONFIG);
  359. gpu_id->b = PVR_CR_FIELD_GET(core_rev, CORE_REVISION_MAJOR);
  360. gpu_id->v = PVR_CR_FIELD_GET(core_rev, CORE_REVISION_MINOR);
  361. gpu_id->n = FIELD_GET(0xFF00, core_id_config);
  362. gpu_id->c = FIELD_GET(0x00FF, core_id_config);
  363. }
  364. }
  365. /**
  366. * pvr_gpuid_decode_string() - Decode the GPU ID from a module input string
  367. *
  368. * Sets the b, v, n, c fields of struct pvr_dev.gpu_id.
  369. *
  370. * @pvr_dev: Target PowerVR device.
  371. * @param_bvnc: GPU ID (BVNC) module parameter.
  372. * @gpu_id: Output to be updated with the GPU ID.
  373. */
  374. VISIBLE_IF_KUNIT int
  375. pvr_gpuid_decode_string(const struct pvr_device *pvr_dev,
  376. const char *param_bvnc, struct pvr_gpu_id *gpu_id)
  377. {
  378. const struct drm_device *drm_dev = &pvr_dev->base;
  379. char str_cpy[PVR_GPUID_STRING_MAX_LENGTH];
  380. char *pos, *tkn;
  381. int ret, idx = 0;
  382. u16 user_bvnc_u16[4];
  383. u8 dot_cnt = 0;
  384. ret = strscpy(str_cpy, param_bvnc);
  385. /*
  386. * strscpy() should return at least a size 7 for the input to be valid.
  387. * Returns -E2BIG for the case when the string is empty or too long.
  388. */
  389. if (ret < PVR_GPUID_STRING_MIN_LENGTH) {
  390. drm_info(drm_dev,
  391. "Invalid size of the input GPU ID (BVNC): %s",
  392. str_cpy);
  393. return -EINVAL;
  394. }
  395. while (*param_bvnc) {
  396. if (*param_bvnc == '.')
  397. dot_cnt++;
  398. param_bvnc++;
  399. }
  400. if (dot_cnt != 3) {
  401. drm_info(drm_dev,
  402. "Invalid format of the input GPU ID (BVNC): %s",
  403. str_cpy);
  404. return -EINVAL;
  405. }
  406. pos = str_cpy;
  407. while ((tkn = strsep(&pos, ".")) != NULL && idx < 4) {
  408. /* kstrtou16() will also handle the case of consecutive dots */
  409. ret = kstrtou16(tkn, 10, &user_bvnc_u16[idx]);
  410. if (ret) {
  411. drm_info(drm_dev,
  412. "Invalid format of the input GPU ID (BVNC): %s",
  413. str_cpy);
  414. return -EINVAL;
  415. }
  416. idx++;
  417. }
  418. gpu_id->b = user_bvnc_u16[0];
  419. gpu_id->v = user_bvnc_u16[1];
  420. gpu_id->n = user_bvnc_u16[2];
  421. gpu_id->c = user_bvnc_u16[3];
  422. return 0;
  423. }
  424. EXPORT_SYMBOL_IF_KUNIT(pvr_gpuid_decode_string);
  425. static bool pvr_exp_hw_support;
  426. module_param_named(exp_hw_support, pvr_exp_hw_support, bool, 0600);
  427. MODULE_PARM_DESC(exp_hw_support, "Bypass runtime checks for fully supported GPU cores. WARNING: enabling this option may result in a buggy, insecure, or otherwise unusable driver.");
  428. /**
  429. * enum pvr_gpu_support_level - The level of support for a gpu_id in the current
  430. * version of the driver.
  431. *
  432. * @PVR_GPU_UNKNOWN: Cores that are unknown to the driver. These may not even exist.
  433. * @PVR_GPU_EXPERIMENTAL: Cores that have experimental support.
  434. * @PVR_GPU_SUPPORTED: Cores that are supported and maintained.
  435. */
  436. enum pvr_gpu_support_level {
  437. PVR_GPU_UNKNOWN,
  438. PVR_GPU_EXPERIMENTAL,
  439. PVR_GPU_SUPPORTED,
  440. };
  441. static enum pvr_gpu_support_level
  442. pvr_gpu_support_level(const struct pvr_gpu_id *gpu_id)
  443. {
  444. switch (pvr_gpu_id_to_packed_bvnc(gpu_id)) {
  445. case PVR_PACKED_BVNC(33, 15, 11, 3):
  446. case PVR_PACKED_BVNC(36, 53, 104, 796):
  447. return PVR_GPU_SUPPORTED;
  448. case PVR_PACKED_BVNC(36, 52, 104, 182):
  449. return PVR_GPU_EXPERIMENTAL;
  450. default:
  451. return PVR_GPU_UNKNOWN;
  452. }
  453. }
  454. static int
  455. pvr_check_gpu_supported(struct pvr_device *pvr_dev,
  456. const struct pvr_gpu_id *gpu_id)
  457. {
  458. struct drm_device *drm_dev = from_pvr_device(pvr_dev);
  459. switch (pvr_gpu_support_level(gpu_id)) {
  460. case PVR_GPU_SUPPORTED:
  461. if (pvr_exp_hw_support)
  462. drm_info(drm_dev, "Module parameter 'exp_hw_support' was set, but this hardware is fully supported by the current driver.");
  463. break;
  464. case PVR_GPU_EXPERIMENTAL:
  465. if (!pvr_exp_hw_support) {
  466. drm_err(drm_dev, "Unsupported GPU! Set 'exp_hw_support' to bypass this check.");
  467. return -ENODEV;
  468. }
  469. drm_warn(drm_dev, "Running on unsupported hardware; you may encounter bugs!");
  470. break;
  471. /* NOTE: This code path may indicate misbehaving hardware. */
  472. case PVR_GPU_UNKNOWN:
  473. default:
  474. if (!pvr_exp_hw_support) {
  475. drm_err(drm_dev, "Unknown GPU! Set 'exp_hw_support' to bypass this check.");
  476. return -ENODEV;
  477. }
  478. drm_warn(drm_dev, "Running on unknown hardware; expect issues.");
  479. break;
  480. }
  481. return 0;
  482. }
  483. static char *pvr_gpuid_override;
  484. module_param_named(gpuid, pvr_gpuid_override, charp, 0400);
  485. MODULE_PARM_DESC(gpuid, "GPU ID (BVNC) to be used instead of the value read from hardware.");
  486. /**
  487. * pvr_load_gpu_id() - Load a PowerVR device's GPU ID (BVNC) from control
  488. * registers or input parameter. The input parameter is processed instead
  489. * of the GPU register if provided.
  490. *
  491. * Sets the arch field of struct pvr_dev.gpu_id.
  492. *
  493. * @pvr_dev: Target PowerVR device.
  494. */
  495. static int
  496. pvr_load_gpu_id(struct pvr_device *pvr_dev)
  497. {
  498. struct pvr_gpu_id *gpu_id = &pvr_dev->gpu_id;
  499. if (!pvr_gpuid_override || !pvr_gpuid_override[0]) {
  500. pvr_gpuid_decode_reg(pvr_dev, gpu_id);
  501. } else {
  502. drm_warn(from_pvr_device(pvr_dev),
  503. "Using custom GPU ID (BVNC) provided by the user!");
  504. int err = pvr_gpuid_decode_string(pvr_dev, pvr_gpuid_override,
  505. gpu_id);
  506. if (err)
  507. return err;
  508. }
  509. return pvr_check_gpu_supported(pvr_dev, gpu_id);
  510. }
  511. /**
  512. * pvr_set_dma_info() - Set PowerVR device DMA information
  513. * @pvr_dev: Target PowerVR device.
  514. *
  515. * Sets the DMA mask and max segment size for the PowerVR device.
  516. *
  517. * Return:
  518. * * 0 on success,
  519. * * Any error returned by PVR_FEATURE_VALUE(), or
  520. * * Any error returned by dma_set_mask().
  521. */
  522. static int
  523. pvr_set_dma_info(struct pvr_device *pvr_dev)
  524. {
  525. struct drm_device *drm_dev = from_pvr_device(pvr_dev);
  526. u16 phys_bus_width;
  527. int err;
  528. err = PVR_FEATURE_VALUE(pvr_dev, phys_bus_width, &phys_bus_width);
  529. if (err) {
  530. drm_err(drm_dev, "Failed to get device physical bus width\n");
  531. return err;
  532. }
  533. err = dma_set_mask(drm_dev->dev, DMA_BIT_MASK(phys_bus_width));
  534. if (err) {
  535. drm_err(drm_dev, "Failed to set DMA mask (err=%d)\n", err);
  536. return err;
  537. }
  538. dma_set_max_seg_size(drm_dev->dev, UINT_MAX);
  539. return 0;
  540. }
  541. /**
  542. * pvr_device_gpu_init() - GPU-specific initialization for a PowerVR device
  543. * @pvr_dev: Target PowerVR device.
  544. *
  545. * The following steps are taken to ensure the device is ready:
  546. *
  547. * 1. Read the hardware version information from control registers,
  548. * 2. Initialise the hardware feature information,
  549. * 3. Setup the device DMA information,
  550. * 4. Setup the device-scoped memory context, and
  551. * 5. Load firmware into the device.
  552. *
  553. * Return:
  554. * * 0 on success,
  555. * * -%ENODEV if the GPU is not supported,
  556. * * Any error returned by pvr_set_dma_info(),
  557. * * Any error returned by pvr_memory_context_init(), or
  558. * * Any error returned by pvr_request_firmware().
  559. */
  560. static int
  561. pvr_device_gpu_init(struct pvr_device *pvr_dev)
  562. {
  563. int err;
  564. err = pvr_load_gpu_id(pvr_dev);
  565. if (err)
  566. return err;
  567. err = pvr_request_firmware(pvr_dev);
  568. if (err)
  569. return err;
  570. err = pvr_fw_validate_init_device_info(pvr_dev);
  571. if (err)
  572. return err;
  573. if (PVR_HAS_FEATURE(pvr_dev, meta))
  574. pvr_dev->fw_dev.processor_type = PVR_FW_PROCESSOR_TYPE_META;
  575. else if (PVR_HAS_FEATURE(pvr_dev, mips))
  576. pvr_dev->fw_dev.processor_type = PVR_FW_PROCESSOR_TYPE_MIPS;
  577. else if (PVR_HAS_FEATURE(pvr_dev, riscv_fw_processor))
  578. pvr_dev->fw_dev.processor_type = PVR_FW_PROCESSOR_TYPE_RISCV;
  579. else
  580. return -EINVAL;
  581. pvr_stream_create_musthave_masks(pvr_dev);
  582. err = pvr_set_dma_info(pvr_dev);
  583. if (err)
  584. return err;
  585. if (pvr_dev->fw_dev.processor_type != PVR_FW_PROCESSOR_TYPE_MIPS) {
  586. pvr_dev->kernel_vm_ctx = pvr_vm_create_context(pvr_dev, false);
  587. if (IS_ERR(pvr_dev->kernel_vm_ctx))
  588. return PTR_ERR(pvr_dev->kernel_vm_ctx);
  589. }
  590. err = pvr_fw_init(pvr_dev);
  591. if (err)
  592. goto err_vm_ctx_put;
  593. return 0;
  594. err_vm_ctx_put:
  595. if (pvr_dev->fw_dev.processor_type != PVR_FW_PROCESSOR_TYPE_MIPS) {
  596. pvr_vm_context_put(pvr_dev->kernel_vm_ctx);
  597. pvr_dev->kernel_vm_ctx = NULL;
  598. }
  599. return err;
  600. }
  601. /**
  602. * pvr_device_gpu_fini() - GPU-specific deinitialization for a PowerVR device
  603. * @pvr_dev: Target PowerVR device.
  604. */
  605. static void
  606. pvr_device_gpu_fini(struct pvr_device *pvr_dev)
  607. {
  608. pvr_fw_fini(pvr_dev);
  609. if (pvr_dev->fw_dev.processor_type != PVR_FW_PROCESSOR_TYPE_MIPS) {
  610. WARN_ON(!pvr_vm_context_put(pvr_dev->kernel_vm_ctx));
  611. pvr_dev->kernel_vm_ctx = NULL;
  612. }
  613. }
  614. /**
  615. * pvr_device_init() - Initialize a PowerVR device
  616. * @pvr_dev: Target PowerVR device.
  617. *
  618. * If this function returns successfully, the device will have been fully
  619. * initialized. Otherwise, any parts of the device initialized before an error
  620. * occurs will be de-initialized before returning.
  621. *
  622. * NOTE: The initialization steps currently taken are the bare minimum required
  623. * to read from the control registers. The device is unlikely to function
  624. * until further initialization steps are added. [This note should be
  625. * removed when that happens.]
  626. *
  627. * Return:
  628. * * 0 on success,
  629. * * Any error returned by pvr_device_reg_init(),
  630. * * Any error returned by pvr_device_clk_init(), or
  631. * * Any error returned by pvr_device_gpu_init().
  632. */
  633. int
  634. pvr_device_init(struct pvr_device *pvr_dev)
  635. {
  636. struct drm_device *drm_dev = from_pvr_device(pvr_dev);
  637. struct device *dev = drm_dev->dev;
  638. int err;
  639. /* Get the platform-specific data based on the compatible string. */
  640. pvr_dev->device_data = of_device_get_match_data(dev);
  641. /* Enable and initialize clocks required for the device to operate. */
  642. err = pvr_device_clk_init(pvr_dev);
  643. if (err)
  644. return err;
  645. err = pvr_dev->device_data->pwr_ops->init(pvr_dev);
  646. if (err)
  647. return err;
  648. /* Explicitly power the GPU so we can access control registers before the FW is booted. */
  649. err = pm_runtime_resume_and_get(dev);
  650. if (err)
  651. return err;
  652. /* Map the control registers into memory. */
  653. err = pvr_device_reg_init(pvr_dev);
  654. if (err)
  655. goto err_pm_runtime_put;
  656. /* Perform GPU-specific initialization steps. */
  657. err = pvr_device_gpu_init(pvr_dev);
  658. if (err)
  659. goto err_pm_runtime_put;
  660. err = pvr_device_irq_init(pvr_dev);
  661. if (err)
  662. goto err_device_gpu_fini;
  663. pm_runtime_put(dev);
  664. return 0;
  665. err_device_gpu_fini:
  666. pvr_device_gpu_fini(pvr_dev);
  667. err_pm_runtime_put:
  668. pm_runtime_put_sync_suspend(dev);
  669. return err;
  670. }
  671. /**
  672. * pvr_device_fini() - Deinitialize a PowerVR device
  673. * @pvr_dev: Target PowerVR device.
  674. */
  675. void
  676. pvr_device_fini(struct pvr_device *pvr_dev)
  677. {
  678. /*
  679. * Deinitialization stages are performed in reverse order compared to
  680. * the initialization stages in pvr_device_init().
  681. */
  682. pvr_device_irq_fini(pvr_dev);
  683. pvr_device_gpu_fini(pvr_dev);
  684. }
  685. bool
  686. pvr_device_has_uapi_quirk(struct pvr_device *pvr_dev, u32 quirk)
  687. {
  688. switch (quirk) {
  689. case 47217:
  690. return PVR_HAS_QUIRK(pvr_dev, 47217);
  691. case 48545:
  692. return PVR_HAS_QUIRK(pvr_dev, 48545);
  693. case 49927:
  694. return PVR_HAS_QUIRK(pvr_dev, 49927);
  695. case 51764:
  696. return PVR_HAS_QUIRK(pvr_dev, 51764);
  697. case 62269:
  698. return PVR_HAS_QUIRK(pvr_dev, 62269);
  699. default:
  700. return false;
  701. };
  702. }
  703. bool
  704. pvr_device_has_uapi_enhancement(struct pvr_device *pvr_dev, u32 enhancement)
  705. {
  706. switch (enhancement) {
  707. case 35421:
  708. return PVR_HAS_ENHANCEMENT(pvr_dev, 35421);
  709. case 42064:
  710. return PVR_HAS_ENHANCEMENT(pvr_dev, 42064);
  711. default:
  712. return false;
  713. };
  714. }
  715. /**
  716. * pvr_device_has_feature() - Look up device feature based on feature definition
  717. * @pvr_dev: Device pointer.
  718. * @feature: Feature to look up. Should be one of %PVR_FEATURE_*.
  719. *
  720. * Returns:
  721. * * %true if feature is present on device, or
  722. * * %false if feature is not present on device.
  723. */
  724. bool
  725. pvr_device_has_feature(struct pvr_device *pvr_dev, u32 feature)
  726. {
  727. switch (feature) {
  728. case PVR_FEATURE_CLUSTER_GROUPING:
  729. return PVR_HAS_FEATURE(pvr_dev, cluster_grouping);
  730. case PVR_FEATURE_COMPUTE_MORTON_CAPABLE:
  731. return PVR_HAS_FEATURE(pvr_dev, compute_morton_capable);
  732. case PVR_FEATURE_FB_CDC_V4:
  733. return PVR_HAS_FEATURE(pvr_dev, fb_cdc_v4);
  734. case PVR_FEATURE_GPU_MULTICORE_SUPPORT:
  735. return PVR_HAS_FEATURE(pvr_dev, gpu_multicore_support);
  736. case PVR_FEATURE_ISP_ZLS_D24_S8_PACKING_OGL_MODE:
  737. return PVR_HAS_FEATURE(pvr_dev, isp_zls_d24_s8_packing_ogl_mode);
  738. case PVR_FEATURE_S7_TOP_INFRASTRUCTURE:
  739. return PVR_HAS_FEATURE(pvr_dev, s7_top_infrastructure);
  740. case PVR_FEATURE_TESSELLATION:
  741. return PVR_HAS_FEATURE(pvr_dev, tessellation);
  742. case PVR_FEATURE_TPU_DM_GLOBAL_REGISTERS:
  743. return PVR_HAS_FEATURE(pvr_dev, tpu_dm_global_registers);
  744. case PVR_FEATURE_VDM_DRAWINDIRECT:
  745. return PVR_HAS_FEATURE(pvr_dev, vdm_drawindirect);
  746. case PVR_FEATURE_VDM_OBJECT_LEVEL_LLS:
  747. return PVR_HAS_FEATURE(pvr_dev, vdm_object_level_lls);
  748. case PVR_FEATURE_ZLS_SUBTILE:
  749. return PVR_HAS_FEATURE(pvr_dev, zls_subtile);
  750. /* Derived features. */
  751. case PVR_FEATURE_CDM_USER_MODE_QUEUE: {
  752. u8 cdm_control_stream_format = 0;
  753. PVR_FEATURE_VALUE(pvr_dev, cdm_control_stream_format, &cdm_control_stream_format);
  754. return (cdm_control_stream_format >= 2 && cdm_control_stream_format <= 4);
  755. }
  756. case PVR_FEATURE_REQUIRES_FB_CDC_ZLS_SETUP:
  757. if (PVR_HAS_FEATURE(pvr_dev, fbcdc_algorithm)) {
  758. u8 fbcdc_algorithm = 0;
  759. PVR_FEATURE_VALUE(pvr_dev, fbcdc_algorithm, &fbcdc_algorithm);
  760. return (fbcdc_algorithm < 3 || PVR_HAS_FEATURE(pvr_dev, fb_cdc_v4));
  761. }
  762. return false;
  763. default:
  764. WARN(true, "Looking up undefined feature %u\n", feature);
  765. return false;
  766. }
  767. }