processor.h 6.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. #ifndef SELFTEST_KVM_PROCESSOR_H
  3. #define SELFTEST_KVM_PROCESSOR_H
  4. #ifndef __ASSEMBLER__
  5. #include "ucall_common.h"
  6. #else
  7. /* general registers */
  8. #define zero $r0
  9. #define ra $r1
  10. #define tp $r2
  11. #define sp $r3
  12. #define a0 $r4
  13. #define a1 $r5
  14. #define a2 $r6
  15. #define a3 $r7
  16. #define a4 $r8
  17. #define a5 $r9
  18. #define a6 $r10
  19. #define a7 $r11
  20. #define t0 $r12
  21. #define t1 $r13
  22. #define t2 $r14
  23. #define t3 $r15
  24. #define t4 $r16
  25. #define t5 $r17
  26. #define t6 $r18
  27. #define t7 $r19
  28. #define t8 $r20
  29. #define u0 $r21
  30. #define fp $r22
  31. #define s0 $r23
  32. #define s1 $r24
  33. #define s2 $r25
  34. #define s3 $r26
  35. #define s4 $r27
  36. #define s5 $r28
  37. #define s6 $r29
  38. #define s7 $r30
  39. #define s8 $r31
  40. #endif
  41. /*
  42. * LoongArch page table entry definition
  43. * Original header file arch/loongarch/include/asm/loongarch.h
  44. */
  45. #define _PAGE_VALID_SHIFT 0
  46. #define _PAGE_DIRTY_SHIFT 1
  47. #define _PAGE_PLV_SHIFT 2 /* 2~3, two bits */
  48. #define PLV_KERN 0
  49. #define PLV_USER 3
  50. #define PLV_MASK 0x3
  51. #define _CACHE_SHIFT 4 /* 4~5, two bits */
  52. #define _PAGE_PRESENT_SHIFT 7
  53. #define _PAGE_WRITE_SHIFT 8
  54. #define _PAGE_VALID BIT_ULL(_PAGE_VALID_SHIFT)
  55. #define _PAGE_PRESENT BIT_ULL(_PAGE_PRESENT_SHIFT)
  56. #define _PAGE_WRITE BIT_ULL(_PAGE_WRITE_SHIFT)
  57. #define _PAGE_DIRTY BIT_ULL(_PAGE_DIRTY_SHIFT)
  58. #define _PAGE_USER (PLV_USER << _PAGE_PLV_SHIFT)
  59. #define __READABLE (_PAGE_VALID)
  60. #define __WRITEABLE (_PAGE_DIRTY | _PAGE_WRITE)
  61. /* Coherent Cached */
  62. #define _CACHE_CC BIT_ULL(_CACHE_SHIFT)
  63. #define PS_4K 0x0000000c
  64. #define PS_16K 0x0000000e
  65. #define PS_64K 0x00000010
  66. #define PS_DEFAULT_SIZE PS_16K
  67. /* LoongArch Basic CSR registers */
  68. #define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */
  69. #define CSR_CRMD_PG_SHIFT 4
  70. #define CSR_CRMD_PG BIT_ULL(CSR_CRMD_PG_SHIFT)
  71. #define CSR_CRMD_IE_SHIFT 2
  72. #define CSR_CRMD_IE BIT_ULL(CSR_CRMD_IE_SHIFT)
  73. #define CSR_CRMD_PLV_SHIFT 0
  74. #define CSR_CRMD_PLV_WIDTH 2
  75. #define CSR_CRMD_PLV (0x3UL << CSR_CRMD_PLV_SHIFT)
  76. #define PLV_MASK 0x3
  77. #define LOONGARCH_CSR_PRMD 0x1
  78. #define LOONGARCH_CSR_EUEN 0x2
  79. #define LOONGARCH_CSR_ECFG 0x4
  80. #define ECFGB_TIMER 11
  81. #define ECFGF_TIMER (BIT_ULL(ECFGB_TIMER))
  82. #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */
  83. #define CSR_ESTAT_EXC_SHIFT 16
  84. #define CSR_ESTAT_EXC_WIDTH 6
  85. #define CSR_ESTAT_EXC (0x3f << CSR_ESTAT_EXC_SHIFT)
  86. #define EXCCODE_INT 0 /* Interrupt */
  87. #define INT_TI 11 /* Timer interrupt*/
  88. #define LOONGARCH_CSR_ERA 0x6 /* ERA */
  89. #define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */
  90. #define LOONGARCH_CSR_EENTRY 0xc
  91. #define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize */
  92. #define CSR_TLBIDX_PS_SHIFT 24
  93. #define CSR_TLBIDX_PS_WIDTH 6
  94. #define CSR_TLBIDX_PS (0x3fUL << CSR_TLBIDX_PS_SHIFT)
  95. #define CSR_TLBIDX_SIZEM 0x3f000000
  96. #define CSR_TLBIDX_SIZE CSR_TLBIDX_PS_SHIFT
  97. #define LOONGARCH_CSR_ASID 0x18 /* ASID */
  98. #define LOONGARCH_CSR_PGDL 0x19
  99. #define LOONGARCH_CSR_PGDH 0x1a
  100. /* Page table base */
  101. #define LOONGARCH_CSR_PGD 0x1b
  102. #define LOONGARCH_CSR_PWCTL0 0x1c
  103. #define LOONGARCH_CSR_PWCTL1 0x1d
  104. #define LOONGARCH_CSR_STLBPGSIZE 0x1e
  105. #define LOONGARCH_CSR_CPUID 0x20
  106. #define LOONGARCH_CSR_KS0 0x30
  107. #define LOONGARCH_CSR_KS1 0x31
  108. #define LOONGARCH_CSR_TMID 0x40
  109. #define LOONGARCH_CSR_TCFG 0x41
  110. #define CSR_TCFG_VAL (BIT_ULL(48) - BIT_ULL(2))
  111. #define CSR_TCFG_PERIOD_SHIFT 1
  112. #define CSR_TCFG_PERIOD (0x1UL << CSR_TCFG_PERIOD_SHIFT)
  113. #define CSR_TCFG_EN (0x1UL)
  114. #define LOONGARCH_CSR_TVAL 0x42
  115. #define LOONGARCH_CSR_TINTCLR 0x44 /* Timer interrupt clear */
  116. #define CSR_TINTCLR_TI_SHIFT 0
  117. #define CSR_TINTCLR_TI (1 << CSR_TINTCLR_TI_SHIFT)
  118. /* TLB refill exception entry */
  119. #define LOONGARCH_CSR_TLBRENTRY 0x88
  120. #define LOONGARCH_CSR_TLBRSAVE 0x8b
  121. #define LOONGARCH_CSR_TLBREHI 0x8e
  122. #define CSR_TLBREHI_PS_SHIFT 0
  123. #define CSR_TLBREHI_PS (0x3fUL << CSR_TLBREHI_PS_SHIFT)
  124. #define csr_read(csr) \
  125. ({ \
  126. register unsigned long __v; \
  127. __asm__ __volatile__( \
  128. "csrrd %[val], %[reg]\n\t" \
  129. : [val] "=r" (__v) \
  130. : [reg] "i" (csr) \
  131. : "memory"); \
  132. __v; \
  133. })
  134. #define csr_write(v, csr) \
  135. ({ \
  136. register unsigned long __v = v; \
  137. __asm__ __volatile__ ( \
  138. "csrwr %[val], %[reg]\n\t" \
  139. : [val] "+r" (__v) \
  140. : [reg] "i" (csr) \
  141. : "memory"); \
  142. __v; \
  143. })
  144. #define EXREGS_GPRS (32)
  145. #ifndef __ASSEMBLER__
  146. void handle_tlb_refill(void);
  147. void handle_exception(void);
  148. struct ex_regs {
  149. unsigned long regs[EXREGS_GPRS];
  150. unsigned long pc;
  151. unsigned long estat;
  152. unsigned long badv;
  153. unsigned long prmd;
  154. };
  155. #define PC_OFFSET_EXREGS offsetof(struct ex_regs, pc)
  156. #define ESTAT_OFFSET_EXREGS offsetof(struct ex_regs, estat)
  157. #define BADV_OFFSET_EXREGS offsetof(struct ex_regs, badv)
  158. #define PRMD_OFFSET_EXREGS offsetof(struct ex_regs, prmd)
  159. #define EXREGS_SIZE sizeof(struct ex_regs)
  160. #define VECTOR_NUM 64
  161. typedef void(*handler_fn)(struct ex_regs *);
  162. struct handlers {
  163. handler_fn exception_handlers[VECTOR_NUM];
  164. };
  165. void vm_init_descriptor_tables(struct kvm_vm *vm);
  166. void vm_install_exception_handler(struct kvm_vm *vm, int vector, handler_fn handler);
  167. static inline void cpu_relax(void)
  168. {
  169. asm volatile("nop" ::: "memory");
  170. }
  171. static inline void local_irq_enable(void)
  172. {
  173. unsigned int flags = CSR_CRMD_IE;
  174. register unsigned int mask asm("$t0") = CSR_CRMD_IE;
  175. __asm__ __volatile__(
  176. "csrxchg %[val], %[mask], %[reg]\n\t"
  177. : [val] "+r" (flags)
  178. : [mask] "r" (mask), [reg] "i" (LOONGARCH_CSR_CRMD)
  179. : "memory");
  180. }
  181. static inline void local_irq_disable(void)
  182. {
  183. unsigned int flags = 0;
  184. register unsigned int mask asm("$t0") = CSR_CRMD_IE;
  185. __asm__ __volatile__(
  186. "csrxchg %[val], %[mask], %[reg]\n\t"
  187. : [val] "+r" (flags)
  188. : [mask] "r" (mask), [reg] "i" (LOONGARCH_CSR_CRMD)
  189. : "memory");
  190. }
  191. #else
  192. #define PC_OFFSET_EXREGS ((EXREGS_GPRS + 0) * 8)
  193. #define ESTAT_OFFSET_EXREGS ((EXREGS_GPRS + 1) * 8)
  194. #define BADV_OFFSET_EXREGS ((EXREGS_GPRS + 2) * 8)
  195. #define PRMD_OFFSET_EXREGS ((EXREGS_GPRS + 3) * 8)
  196. #define EXREGS_SIZE ((EXREGS_GPRS + 4) * 8)
  197. #endif
  198. #endif /* SELFTEST_KVM_PROCESSOR_H */