ofdrm.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. #include <linux/aperture.h>
  3. #include <linux/of_address.h>
  4. #include <linux/pci.h>
  5. #include <linux/platform_device.h>
  6. #include <drm/clients/drm_client_setup.h>
  7. #include <drm/drm_atomic.h>
  8. #include <drm/drm_atomic_state_helper.h>
  9. #include <drm/drm_color_mgmt.h>
  10. #include <drm/drm_connector.h>
  11. #include <drm/drm_damage_helper.h>
  12. #include <drm/drm_device.h>
  13. #include <drm/drm_drv.h>
  14. #include <drm/drm_edid.h>
  15. #include <drm/drm_fbdev_shmem.h>
  16. #include <drm/drm_framebuffer.h>
  17. #include <drm/drm_gem_atomic_helper.h>
  18. #include <drm/drm_gem_framebuffer_helper.h>
  19. #include <drm/drm_gem_shmem_helper.h>
  20. #include <drm/drm_managed.h>
  21. #include <drm/drm_modeset_helper_vtables.h>
  22. #include <drm/drm_print.h>
  23. #include <drm/drm_probe_helper.h>
  24. #include "drm_sysfb_helper.h"
  25. #define DRIVER_NAME "ofdrm"
  26. #define DRIVER_DESC "DRM driver for OF platform devices"
  27. #define DRIVER_MAJOR 1
  28. #define DRIVER_MINOR 0
  29. #define PCI_VENDOR_ID_ATI_R520 0x7100
  30. #define PCI_VENDOR_ID_ATI_R600 0x9400
  31. #define OFDRM_GAMMA_LUT_SIZE 256
  32. /* Definitions used by the Avivo palette */
  33. #define AVIVO_DC_LUT_RW_SELECT 0x6480
  34. #define AVIVO_DC_LUT_RW_MODE 0x6484
  35. #define AVIVO_DC_LUT_RW_INDEX 0x6488
  36. #define AVIVO_DC_LUT_SEQ_COLOR 0x648c
  37. #define AVIVO_DC_LUT_PWL_DATA 0x6490
  38. #define AVIVO_DC_LUT_30_COLOR 0x6494
  39. #define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498
  40. #define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c
  41. #define AVIVO_DC_LUT_AUTOFILL 0x64a0
  42. #define AVIVO_DC_LUTA_CONTROL 0x64c0
  43. #define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4
  44. #define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8
  45. #define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc
  46. #define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0
  47. #define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
  48. #define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
  49. #define AVIVO_DC_LUTB_CONTROL 0x6cc0
  50. #define AVIVO_DC_LUTB_BLACK_OFFSET_BLUE 0x6cc4
  51. #define AVIVO_DC_LUTB_BLACK_OFFSET_GREEN 0x6cc8
  52. #define AVIVO_DC_LUTB_BLACK_OFFSET_RED 0x6ccc
  53. #define AVIVO_DC_LUTB_WHITE_OFFSET_BLUE 0x6cd0
  54. #define AVIVO_DC_LUTB_WHITE_OFFSET_GREEN 0x6cd4
  55. #define AVIVO_DC_LUTB_WHITE_OFFSET_RED 0x6cd8
  56. enum ofdrm_model {
  57. OFDRM_MODEL_UNKNOWN,
  58. OFDRM_MODEL_MACH64, /* ATI Mach64 */
  59. OFDRM_MODEL_RAGE128, /* ATI Rage128 */
  60. OFDRM_MODEL_RAGE_M3A, /* ATI Rage Mobility M3 Head A */
  61. OFDRM_MODEL_RAGE_M3B, /* ATI Rage Mobility M3 Head B */
  62. OFDRM_MODEL_RADEON, /* ATI Radeon */
  63. OFDRM_MODEL_GXT2000, /* IBM GXT2000 */
  64. OFDRM_MODEL_AVIVO, /* ATI R5xx */
  65. OFDRM_MODEL_QEMU, /* QEMU VGA */
  66. };
  67. /*
  68. * Helpers for display nodes
  69. */
  70. static int display_get_validated_int(struct drm_device *dev, const char *name, uint32_t value)
  71. {
  72. return drm_sysfb_get_validated_int(dev, name, value, INT_MAX);
  73. }
  74. static int display_get_validated_int0(struct drm_device *dev, const char *name, uint32_t value)
  75. {
  76. return drm_sysfb_get_validated_int0(dev, name, value, INT_MAX);
  77. }
  78. static const struct drm_format_info *display_get_validated_format(struct drm_device *dev,
  79. u32 depth, bool big_endian)
  80. {
  81. const struct drm_format_info *info;
  82. u32 format;
  83. switch (depth) {
  84. case 8:
  85. format = drm_mode_legacy_fb_format(8, 8);
  86. break;
  87. case 15:
  88. case 16:
  89. format = drm_mode_legacy_fb_format(16, depth);
  90. break;
  91. case 32:
  92. format = drm_mode_legacy_fb_format(32, 24);
  93. break;
  94. default:
  95. drm_err(dev, "unsupported framebuffer depth %u\n", depth);
  96. return ERR_PTR(-EINVAL);
  97. }
  98. /*
  99. * DRM formats assume little-endian byte order. Update the format
  100. * if the scanout buffer uses big-endian ordering.
  101. */
  102. if (big_endian) {
  103. switch (format) {
  104. case DRM_FORMAT_XRGB8888:
  105. format = DRM_FORMAT_BGRX8888;
  106. break;
  107. case DRM_FORMAT_ARGB8888:
  108. format = DRM_FORMAT_BGRA8888;
  109. break;
  110. case DRM_FORMAT_RGB565:
  111. format = DRM_FORMAT_RGB565 | DRM_FORMAT_BIG_ENDIAN;
  112. break;
  113. case DRM_FORMAT_XRGB1555:
  114. format = DRM_FORMAT_XRGB1555 | DRM_FORMAT_BIG_ENDIAN;
  115. break;
  116. default:
  117. break;
  118. }
  119. }
  120. info = drm_format_info(format);
  121. if (!info) {
  122. drm_err(dev, "cannot find framebuffer format for depth %u\n", depth);
  123. return ERR_PTR(-EINVAL);
  124. }
  125. return info;
  126. }
  127. static int display_read_u32_of(struct drm_device *dev, struct device_node *of_node,
  128. const char *name, u32 *value)
  129. {
  130. int ret = of_property_read_u32(of_node, name, value);
  131. if (ret)
  132. drm_err(dev, "cannot parse framebuffer %s: error %d\n", name, ret);
  133. return ret;
  134. }
  135. static bool display_get_big_endian_of(struct drm_device *dev, struct device_node *of_node)
  136. {
  137. bool big_endian;
  138. #ifdef __BIG_ENDIAN
  139. big_endian = !of_property_read_bool(of_node, "little-endian");
  140. #else
  141. big_endian = of_property_read_bool(of_node, "big-endian");
  142. #endif
  143. return big_endian;
  144. }
  145. static int display_get_width_of(struct drm_device *dev, struct device_node *of_node)
  146. {
  147. u32 width;
  148. int ret = display_read_u32_of(dev, of_node, "width", &width);
  149. if (ret)
  150. return ret;
  151. return display_get_validated_int0(dev, "width", width);
  152. }
  153. static int display_get_height_of(struct drm_device *dev, struct device_node *of_node)
  154. {
  155. u32 height;
  156. int ret = display_read_u32_of(dev, of_node, "height", &height);
  157. if (ret)
  158. return ret;
  159. return display_get_validated_int0(dev, "height", height);
  160. }
  161. static int display_get_depth_of(struct drm_device *dev, struct device_node *of_node)
  162. {
  163. u32 depth;
  164. int ret = display_read_u32_of(dev, of_node, "depth", &depth);
  165. if (ret)
  166. return ret;
  167. return display_get_validated_int0(dev, "depth", depth);
  168. }
  169. static int display_get_linebytes_of(struct drm_device *dev, struct device_node *of_node)
  170. {
  171. u32 linebytes;
  172. int ret = display_read_u32_of(dev, of_node, "linebytes", &linebytes);
  173. if (ret)
  174. return ret;
  175. return display_get_validated_int(dev, "linebytes", linebytes);
  176. }
  177. static u64 display_get_address_of(struct drm_device *dev, struct device_node *of_node)
  178. {
  179. u32 address;
  180. int ret;
  181. /*
  182. * Not all devices provide an address property, it's not
  183. * a bug if this fails. The driver will try to find the
  184. * framebuffer base address from the device's memory regions.
  185. */
  186. ret = of_property_read_u32(of_node, "address", &address);
  187. if (ret)
  188. return OF_BAD_ADDR;
  189. return address;
  190. }
  191. static const u8 *display_get_edid_of(struct drm_device *dev, struct device_node *of_node,
  192. u8 buf[EDID_LENGTH])
  193. {
  194. int ret = of_property_read_u8_array(of_node, "EDID", buf, EDID_LENGTH);
  195. if (ret)
  196. return NULL;
  197. return buf;
  198. }
  199. static bool is_avivo(u32 vendor, u32 device)
  200. {
  201. /* This will match most R5xx */
  202. return (vendor == PCI_VENDOR_ID_ATI) &&
  203. ((device >= PCI_VENDOR_ID_ATI_R520 && device < 0x7800) ||
  204. (PCI_VENDOR_ID_ATI_R600 >= 0x9400));
  205. }
  206. static enum ofdrm_model display_get_model_of(struct drm_device *dev, struct device_node *of_node)
  207. {
  208. enum ofdrm_model model = OFDRM_MODEL_UNKNOWN;
  209. if (of_node_name_prefix(of_node, "ATY,Rage128")) {
  210. model = OFDRM_MODEL_RAGE128;
  211. } else if (of_node_name_prefix(of_node, "ATY,RageM3pA") ||
  212. of_node_name_prefix(of_node, "ATY,RageM3p12A")) {
  213. model = OFDRM_MODEL_RAGE_M3A;
  214. } else if (of_node_name_prefix(of_node, "ATY,RageM3pB")) {
  215. model = OFDRM_MODEL_RAGE_M3B;
  216. } else if (of_node_name_prefix(of_node, "ATY,Rage6")) {
  217. model = OFDRM_MODEL_RADEON;
  218. } else if (of_node_name_prefix(of_node, "ATY,")) {
  219. return OFDRM_MODEL_MACH64;
  220. } else if (of_device_is_compatible(of_node, "pci1014,b7") ||
  221. of_device_is_compatible(of_node, "pci1014,21c")) {
  222. model = OFDRM_MODEL_GXT2000;
  223. } else if (of_node_name_prefix(of_node, "vga,Display-")) {
  224. struct device_node *of_parent;
  225. const __be32 *vendor_p, *device_p;
  226. /* Look for AVIVO initialized by SLOF */
  227. of_parent = of_get_parent(of_node);
  228. vendor_p = of_get_property(of_parent, "vendor-id", NULL);
  229. device_p = of_get_property(of_parent, "device-id", NULL);
  230. if (vendor_p && device_p) {
  231. u32 vendor = be32_to_cpup(vendor_p);
  232. u32 device = be32_to_cpup(device_p);
  233. if (is_avivo(vendor, device))
  234. model = OFDRM_MODEL_AVIVO;
  235. }
  236. of_node_put(of_parent);
  237. } else if (of_device_is_compatible(of_node, "qemu,std-vga")) {
  238. model = OFDRM_MODEL_QEMU;
  239. }
  240. return model;
  241. }
  242. /*
  243. * Open Firmware display device
  244. */
  245. struct ofdrm_device;
  246. struct ofdrm_device_funcs {
  247. void __iomem *(*cmap_ioremap)(struct ofdrm_device *odev,
  248. struct device_node *of_node,
  249. u64 fb_bas);
  250. void (*cmap_write)(struct ofdrm_device *odev, unsigned char index,
  251. unsigned char r, unsigned char g, unsigned char b);
  252. };
  253. struct ofdrm_device {
  254. struct drm_sysfb_device sysfb;
  255. const struct ofdrm_device_funcs *funcs;
  256. /* colormap */
  257. void __iomem *cmap_base;
  258. u8 edid[EDID_LENGTH];
  259. /* modesetting */
  260. u32 formats[DRM_SYSFB_PLANE_NFORMATS(1)];
  261. struct drm_plane primary_plane;
  262. struct drm_crtc crtc;
  263. struct drm_encoder encoder;
  264. struct drm_connector connector;
  265. };
  266. static struct ofdrm_device *ofdrm_device_of_dev(struct drm_device *dev)
  267. {
  268. return container_of(to_drm_sysfb_device(dev), struct ofdrm_device, sysfb);
  269. }
  270. /*
  271. * Hardware
  272. */
  273. #if defined(CONFIG_PCI)
  274. static struct pci_dev *display_get_pci_dev_of(struct drm_device *dev, struct device_node *of_node)
  275. {
  276. const __be32 *vendor_p, *device_p;
  277. u32 vendor, device;
  278. struct pci_dev *pcidev;
  279. vendor_p = of_get_property(of_node, "vendor-id", NULL);
  280. if (!vendor_p)
  281. return ERR_PTR(-ENODEV);
  282. vendor = be32_to_cpup(vendor_p);
  283. device_p = of_get_property(of_node, "device-id", NULL);
  284. if (!device_p)
  285. return ERR_PTR(-ENODEV);
  286. device = be32_to_cpup(device_p);
  287. pcidev = pci_get_device(vendor, device, NULL);
  288. if (!pcidev)
  289. return ERR_PTR(-ENODEV);
  290. return pcidev;
  291. }
  292. static void ofdrm_pci_release(void *data)
  293. {
  294. struct pci_dev *pcidev = data;
  295. pci_disable_device(pcidev);
  296. }
  297. static int ofdrm_device_init_pci(struct ofdrm_device *odev)
  298. {
  299. struct drm_device *dev = &odev->sysfb.dev;
  300. struct platform_device *pdev = to_platform_device(dev->dev);
  301. struct device_node *of_node = pdev->dev.of_node;
  302. struct pci_dev *pcidev;
  303. int ret;
  304. /*
  305. * Never use pcim_ or other managed helpers on the returned PCI
  306. * device. Otherwise, probing the native driver will fail for
  307. * resource conflicts. PCI-device management has to be tied to
  308. * the lifetime of the platform device until the native driver
  309. * takes over.
  310. */
  311. pcidev = display_get_pci_dev_of(dev, of_node);
  312. if (IS_ERR(pcidev))
  313. return 0; /* no PCI device found; ignore the error */
  314. ret = pci_enable_device(pcidev);
  315. if (ret) {
  316. drm_err(dev, "pci_enable_device(%s) failed: %d\n",
  317. dev_name(&pcidev->dev), ret);
  318. return ret;
  319. }
  320. ret = devm_add_action_or_reset(&pdev->dev, ofdrm_pci_release, pcidev);
  321. if (ret)
  322. return ret;
  323. return 0;
  324. }
  325. #else
  326. static int ofdrm_device_init_pci(struct ofdrm_device *odev)
  327. {
  328. return 0;
  329. }
  330. #endif
  331. /*
  332. * OF display settings
  333. */
  334. static struct resource *ofdrm_find_fb_resource(struct ofdrm_device *odev,
  335. struct resource *fb_res)
  336. {
  337. struct platform_device *pdev = to_platform_device(odev->sysfb.dev.dev);
  338. struct resource *res, *max_res = NULL;
  339. u32 i;
  340. for (i = 0; pdev->num_resources; ++i) {
  341. res = platform_get_resource(pdev, IORESOURCE_MEM, i);
  342. if (!res)
  343. break; /* all resources processed */
  344. if (resource_size(res) < resource_size(fb_res))
  345. continue; /* resource too small */
  346. if (fb_res->start && resource_contains(res, fb_res))
  347. return res; /* resource contains framebuffer */
  348. if (!max_res || resource_size(res) > resource_size(max_res))
  349. max_res = res; /* store largest resource as fallback */
  350. }
  351. return max_res;
  352. }
  353. /*
  354. * Colormap / Palette
  355. */
  356. static void __iomem *get_cmap_address_of(struct ofdrm_device *odev, struct device_node *of_node,
  357. int bar_no, unsigned long offset, unsigned long size)
  358. {
  359. struct drm_device *dev = &odev->sysfb.dev;
  360. const __be32 *addr_p;
  361. u64 max_size, address;
  362. unsigned int flags;
  363. void __iomem *mem;
  364. addr_p = of_get_pci_address(of_node, bar_no, &max_size, &flags);
  365. if (!addr_p)
  366. addr_p = of_get_address(of_node, bar_no, &max_size, &flags);
  367. if (!addr_p)
  368. return IOMEM_ERR_PTR(-ENODEV);
  369. if ((flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
  370. return IOMEM_ERR_PTR(-ENODEV);
  371. if ((offset + size) >= max_size)
  372. return IOMEM_ERR_PTR(-ENODEV);
  373. address = of_translate_address(of_node, addr_p);
  374. if (address == OF_BAD_ADDR)
  375. return IOMEM_ERR_PTR(-ENODEV);
  376. mem = devm_ioremap(dev->dev, address + offset, size);
  377. if (!mem)
  378. return IOMEM_ERR_PTR(-ENOMEM);
  379. return mem;
  380. }
  381. static void __iomem *ofdrm_mach64_cmap_ioremap(struct ofdrm_device *odev,
  382. struct device_node *of_node,
  383. u64 fb_base)
  384. {
  385. struct drm_device *dev = &odev->sysfb.dev;
  386. u64 address;
  387. void __iomem *cmap_base;
  388. address = fb_base & 0xff000000ul;
  389. address += 0x7ff000;
  390. cmap_base = devm_ioremap(dev->dev, address, 0x1000);
  391. if (!cmap_base)
  392. return IOMEM_ERR_PTR(-ENOMEM);
  393. return cmap_base;
  394. }
  395. static void ofdrm_mach64_cmap_write(struct ofdrm_device *odev, unsigned char index,
  396. unsigned char r, unsigned char g, unsigned char b)
  397. {
  398. void __iomem *addr = odev->cmap_base + 0xcc0;
  399. void __iomem *data = odev->cmap_base + 0xcc0 + 1;
  400. writeb(index, addr);
  401. writeb(r, data);
  402. writeb(g, data);
  403. writeb(b, data);
  404. }
  405. static void __iomem *ofdrm_rage128_cmap_ioremap(struct ofdrm_device *odev,
  406. struct device_node *of_node,
  407. u64 fb_base)
  408. {
  409. return get_cmap_address_of(odev, of_node, 2, 0, 0x1fff);
  410. }
  411. static void ofdrm_rage128_cmap_write(struct ofdrm_device *odev, unsigned char index,
  412. unsigned char r, unsigned char g, unsigned char b)
  413. {
  414. void __iomem *addr = odev->cmap_base + 0xb0;
  415. void __iomem *data = odev->cmap_base + 0xb4;
  416. u32 color = (r << 16) | (g << 8) | b;
  417. writeb(index, addr);
  418. writel(color, data);
  419. }
  420. static void __iomem *ofdrm_rage_m3a_cmap_ioremap(struct ofdrm_device *odev,
  421. struct device_node *of_node,
  422. u64 fb_base)
  423. {
  424. return get_cmap_address_of(odev, of_node, 2, 0, 0x1fff);
  425. }
  426. static void ofdrm_rage_m3a_cmap_write(struct ofdrm_device *odev, unsigned char index,
  427. unsigned char r, unsigned char g, unsigned char b)
  428. {
  429. void __iomem *dac_ctl = odev->cmap_base + 0x58;
  430. void __iomem *addr = odev->cmap_base + 0xb0;
  431. void __iomem *data = odev->cmap_base + 0xb4;
  432. u32 color = (r << 16) | (g << 8) | b;
  433. u32 val;
  434. /* Clear PALETTE_ACCESS_CNTL in DAC_CNTL */
  435. val = readl(dac_ctl);
  436. val &= ~0x20;
  437. writel(val, dac_ctl);
  438. /* Set color at palette index */
  439. writeb(index, addr);
  440. writel(color, data);
  441. }
  442. static void __iomem *ofdrm_rage_m3b_cmap_ioremap(struct ofdrm_device *odev,
  443. struct device_node *of_node,
  444. u64 fb_base)
  445. {
  446. return get_cmap_address_of(odev, of_node, 2, 0, 0x1fff);
  447. }
  448. static void ofdrm_rage_m3b_cmap_write(struct ofdrm_device *odev, unsigned char index,
  449. unsigned char r, unsigned char g, unsigned char b)
  450. {
  451. void __iomem *dac_ctl = odev->cmap_base + 0x58;
  452. void __iomem *addr = odev->cmap_base + 0xb0;
  453. void __iomem *data = odev->cmap_base + 0xb4;
  454. u32 color = (r << 16) | (g << 8) | b;
  455. u32 val;
  456. /* Set PALETTE_ACCESS_CNTL in DAC_CNTL */
  457. val = readl(dac_ctl);
  458. val |= 0x20;
  459. writel(val, dac_ctl);
  460. /* Set color at palette index */
  461. writeb(index, addr);
  462. writel(color, data);
  463. }
  464. static void __iomem *ofdrm_radeon_cmap_ioremap(struct ofdrm_device *odev,
  465. struct device_node *of_node,
  466. u64 fb_base)
  467. {
  468. return get_cmap_address_of(odev, of_node, 1, 0, 0x1fff);
  469. }
  470. static void __iomem *ofdrm_gxt2000_cmap_ioremap(struct ofdrm_device *odev,
  471. struct device_node *of_node,
  472. u64 fb_base)
  473. {
  474. return get_cmap_address_of(odev, of_node, 0, 0x6000, 0x1000);
  475. }
  476. static void ofdrm_gxt2000_cmap_write(struct ofdrm_device *odev, unsigned char index,
  477. unsigned char r, unsigned char g, unsigned char b)
  478. {
  479. void __iomem *data = ((unsigned int __iomem *)odev->cmap_base) + index;
  480. u32 color = (r << 16) | (g << 8) | b;
  481. writel(color, data);
  482. }
  483. static void __iomem *ofdrm_avivo_cmap_ioremap(struct ofdrm_device *odev,
  484. struct device_node *of_node,
  485. u64 fb_base)
  486. {
  487. struct device_node *of_parent;
  488. void __iomem *cmap_base;
  489. of_parent = of_get_parent(of_node);
  490. cmap_base = get_cmap_address_of(odev, of_parent, 0, 0, 0x10000);
  491. of_node_put(of_parent);
  492. return cmap_base;
  493. }
  494. static void ofdrm_avivo_cmap_write(struct ofdrm_device *odev, unsigned char index,
  495. unsigned char r, unsigned char g, unsigned char b)
  496. {
  497. void __iomem *lutsel = odev->cmap_base + AVIVO_DC_LUT_RW_SELECT;
  498. void __iomem *addr = odev->cmap_base + AVIVO_DC_LUT_RW_INDEX;
  499. void __iomem *data = odev->cmap_base + AVIVO_DC_LUT_30_COLOR;
  500. u32 color = (r << 22) | (g << 12) | (b << 2);
  501. /* Write to both LUTs for now */
  502. writel(1, lutsel);
  503. writeb(index, addr);
  504. writel(color, data);
  505. writel(0, lutsel);
  506. writeb(index, addr);
  507. writel(color, data);
  508. }
  509. static void __iomem *ofdrm_qemu_cmap_ioremap(struct ofdrm_device *odev,
  510. struct device_node *of_node,
  511. u64 fb_base)
  512. {
  513. static const __be32 io_of_addr[3] = {
  514. cpu_to_be32(0x01000000),
  515. cpu_to_be32(0x00),
  516. cpu_to_be32(0x00),
  517. };
  518. struct drm_device *dev = &odev->sysfb.dev;
  519. u64 address;
  520. void __iomem *cmap_base;
  521. address = of_translate_address(of_node, io_of_addr);
  522. if (address == OF_BAD_ADDR)
  523. return IOMEM_ERR_PTR(-ENODEV);
  524. cmap_base = devm_ioremap(dev->dev, address + 0x3c8, 2);
  525. if (!cmap_base)
  526. return IOMEM_ERR_PTR(-ENOMEM);
  527. return cmap_base;
  528. }
  529. static void ofdrm_qemu_cmap_write(struct ofdrm_device *odev, unsigned char index,
  530. unsigned char r, unsigned char g, unsigned char b)
  531. {
  532. void __iomem *addr = odev->cmap_base;
  533. void __iomem *data = odev->cmap_base + 1;
  534. writeb(index, addr);
  535. writeb(r, data);
  536. writeb(g, data);
  537. writeb(b, data);
  538. }
  539. static void ofdrm_set_gamma_lut(struct drm_crtc *crtc, unsigned int index,
  540. u16 red, u16 green, u16 blue)
  541. {
  542. struct drm_device *dev = crtc->dev;
  543. struct ofdrm_device *odev = ofdrm_device_of_dev(dev);
  544. u8 i8 = index & 0xff;
  545. u8 r8 = red >> 8;
  546. u8 g8 = green >> 8;
  547. u8 b8 = blue >> 8;
  548. if (drm_WARN_ON_ONCE(dev, index != i8))
  549. return; /* driver bug */
  550. odev->funcs->cmap_write(odev, i8, r8, g8, b8);
  551. }
  552. static void ofdrm_device_fill_gamma(struct ofdrm_device *odev,
  553. const struct drm_format_info *format)
  554. {
  555. struct drm_device *dev = &odev->sysfb.dev;
  556. struct drm_crtc *crtc = &odev->crtc;
  557. switch (format->format) {
  558. case DRM_FORMAT_RGB565:
  559. case DRM_FORMAT_RGB565 | DRM_FORMAT_BIG_ENDIAN:
  560. drm_crtc_fill_gamma_565(crtc, ofdrm_set_gamma_lut);
  561. break;
  562. case DRM_FORMAT_XRGB8888:
  563. case DRM_FORMAT_BGRX8888:
  564. drm_crtc_fill_gamma_888(crtc, ofdrm_set_gamma_lut);
  565. break;
  566. default:
  567. drm_warn_once(dev, "Unsupported format %p4cc for gamma correction\n",
  568. &format->format);
  569. break;
  570. }
  571. }
  572. static void ofdrm_device_load_gamma(struct ofdrm_device *odev,
  573. const struct drm_format_info *format,
  574. struct drm_color_lut *lut)
  575. {
  576. struct drm_device *dev = &odev->sysfb.dev;
  577. struct drm_crtc *crtc = &odev->crtc;
  578. switch (format->format) {
  579. case DRM_FORMAT_RGB565:
  580. case DRM_FORMAT_RGB565 | DRM_FORMAT_BIG_ENDIAN:
  581. drm_crtc_load_gamma_565_from_888(crtc, lut, ofdrm_set_gamma_lut);
  582. break;
  583. case DRM_FORMAT_XRGB8888:
  584. case DRM_FORMAT_BGRX8888:
  585. drm_crtc_load_gamma_888(crtc, lut, ofdrm_set_gamma_lut);
  586. break;
  587. default:
  588. drm_warn_once(dev, "Unsupported format %p4cc for gamma correction\n",
  589. &format->format);
  590. break;
  591. }
  592. }
  593. /*
  594. * Modesetting
  595. */
  596. static const u64 ofdrm_primary_plane_format_modifiers[] = {
  597. DRM_SYSFB_PLANE_FORMAT_MODIFIERS,
  598. };
  599. static const struct drm_plane_helper_funcs ofdrm_primary_plane_helper_funcs = {
  600. DRM_SYSFB_PLANE_HELPER_FUNCS,
  601. };
  602. static const struct drm_plane_funcs ofdrm_primary_plane_funcs = {
  603. DRM_SYSFB_PLANE_FUNCS,
  604. .destroy = drm_plane_cleanup,
  605. };
  606. static void ofdrm_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state)
  607. {
  608. struct ofdrm_device *odev = ofdrm_device_of_dev(crtc->dev);
  609. struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
  610. struct drm_sysfb_crtc_state *sysfb_crtc_state = to_drm_sysfb_crtc_state(crtc_state);
  611. if (crtc_state->enable && crtc_state->color_mgmt_changed) {
  612. const struct drm_format_info *format = sysfb_crtc_state->format;
  613. if (crtc_state->gamma_lut)
  614. ofdrm_device_load_gamma(odev, format, crtc_state->gamma_lut->data);
  615. else
  616. ofdrm_device_fill_gamma(odev, format);
  617. }
  618. }
  619. static const struct drm_crtc_helper_funcs ofdrm_crtc_helper_funcs = {
  620. DRM_SYSFB_CRTC_HELPER_FUNCS,
  621. .atomic_flush = ofdrm_crtc_helper_atomic_flush,
  622. };
  623. static const struct drm_crtc_funcs ofdrm_crtc_funcs = {
  624. DRM_SYSFB_CRTC_FUNCS,
  625. .destroy = drm_crtc_cleanup,
  626. };
  627. static const struct drm_encoder_funcs ofdrm_encoder_funcs = {
  628. .destroy = drm_encoder_cleanup,
  629. };
  630. static const struct drm_connector_helper_funcs ofdrm_connector_helper_funcs = {
  631. DRM_SYSFB_CONNECTOR_HELPER_FUNCS,
  632. };
  633. static const struct drm_connector_funcs ofdrm_connector_funcs = {
  634. DRM_SYSFB_CONNECTOR_FUNCS,
  635. .destroy = drm_connector_cleanup,
  636. };
  637. static const struct drm_mode_config_funcs ofdrm_mode_config_funcs = {
  638. DRM_SYSFB_MODE_CONFIG_FUNCS,
  639. };
  640. /*
  641. * Init / Cleanup
  642. */
  643. static const struct ofdrm_device_funcs ofdrm_unknown_device_funcs = {
  644. };
  645. static const struct ofdrm_device_funcs ofdrm_mach64_device_funcs = {
  646. .cmap_ioremap = ofdrm_mach64_cmap_ioremap,
  647. .cmap_write = ofdrm_mach64_cmap_write,
  648. };
  649. static const struct ofdrm_device_funcs ofdrm_rage128_device_funcs = {
  650. .cmap_ioremap = ofdrm_rage128_cmap_ioremap,
  651. .cmap_write = ofdrm_rage128_cmap_write,
  652. };
  653. static const struct ofdrm_device_funcs ofdrm_rage_m3a_device_funcs = {
  654. .cmap_ioremap = ofdrm_rage_m3a_cmap_ioremap,
  655. .cmap_write = ofdrm_rage_m3a_cmap_write,
  656. };
  657. static const struct ofdrm_device_funcs ofdrm_rage_m3b_device_funcs = {
  658. .cmap_ioremap = ofdrm_rage_m3b_cmap_ioremap,
  659. .cmap_write = ofdrm_rage_m3b_cmap_write,
  660. };
  661. static const struct ofdrm_device_funcs ofdrm_radeon_device_funcs = {
  662. .cmap_ioremap = ofdrm_radeon_cmap_ioremap,
  663. .cmap_write = ofdrm_rage128_cmap_write, /* same as Rage128 */
  664. };
  665. static const struct ofdrm_device_funcs ofdrm_gxt2000_device_funcs = {
  666. .cmap_ioremap = ofdrm_gxt2000_cmap_ioremap,
  667. .cmap_write = ofdrm_gxt2000_cmap_write,
  668. };
  669. static const struct ofdrm_device_funcs ofdrm_avivo_device_funcs = {
  670. .cmap_ioremap = ofdrm_avivo_cmap_ioremap,
  671. .cmap_write = ofdrm_avivo_cmap_write,
  672. };
  673. static const struct ofdrm_device_funcs ofdrm_qemu_device_funcs = {
  674. .cmap_ioremap = ofdrm_qemu_cmap_ioremap,
  675. .cmap_write = ofdrm_qemu_cmap_write,
  676. };
  677. static struct ofdrm_device *ofdrm_device_create(struct drm_driver *drv,
  678. struct platform_device *pdev)
  679. {
  680. struct device_node *of_node = pdev->dev.of_node;
  681. struct ofdrm_device *odev;
  682. struct drm_sysfb_device *sysfb;
  683. struct drm_device *dev;
  684. enum ofdrm_model model;
  685. bool big_endian;
  686. int width, height, depth, linebytes;
  687. const struct drm_format_info *format;
  688. u64 address;
  689. const u8 *edid;
  690. resource_size_t fb_size, fb_base, fb_pgbase, fb_pgsize;
  691. struct resource *res, *mem;
  692. void __iomem *screen_base;
  693. struct drm_plane *primary_plane;
  694. struct drm_crtc *crtc;
  695. struct drm_encoder *encoder;
  696. struct drm_connector *connector;
  697. unsigned long max_width, max_height;
  698. size_t nformats;
  699. int ret;
  700. odev = devm_drm_dev_alloc(&pdev->dev, drv, struct ofdrm_device, sysfb.dev);
  701. if (IS_ERR(odev))
  702. return ERR_CAST(odev);
  703. sysfb = &odev->sysfb;
  704. dev = &sysfb->dev;
  705. platform_set_drvdata(pdev, dev);
  706. ret = ofdrm_device_init_pci(odev);
  707. if (ret)
  708. return ERR_PTR(ret);
  709. /*
  710. * OF display-node settings
  711. */
  712. model = display_get_model_of(dev, of_node);
  713. drm_dbg(dev, "detected model %d\n", model);
  714. switch (model) {
  715. case OFDRM_MODEL_UNKNOWN:
  716. odev->funcs = &ofdrm_unknown_device_funcs;
  717. break;
  718. case OFDRM_MODEL_MACH64:
  719. odev->funcs = &ofdrm_mach64_device_funcs;
  720. break;
  721. case OFDRM_MODEL_RAGE128:
  722. odev->funcs = &ofdrm_rage128_device_funcs;
  723. break;
  724. case OFDRM_MODEL_RAGE_M3A:
  725. odev->funcs = &ofdrm_rage_m3a_device_funcs;
  726. break;
  727. case OFDRM_MODEL_RAGE_M3B:
  728. odev->funcs = &ofdrm_rage_m3b_device_funcs;
  729. break;
  730. case OFDRM_MODEL_RADEON:
  731. odev->funcs = &ofdrm_radeon_device_funcs;
  732. break;
  733. case OFDRM_MODEL_GXT2000:
  734. odev->funcs = &ofdrm_gxt2000_device_funcs;
  735. break;
  736. case OFDRM_MODEL_AVIVO:
  737. odev->funcs = &ofdrm_avivo_device_funcs;
  738. break;
  739. case OFDRM_MODEL_QEMU:
  740. odev->funcs = &ofdrm_qemu_device_funcs;
  741. break;
  742. }
  743. big_endian = display_get_big_endian_of(dev, of_node);
  744. width = display_get_width_of(dev, of_node);
  745. if (width < 0)
  746. return ERR_PTR(width);
  747. height = display_get_height_of(dev, of_node);
  748. if (height < 0)
  749. return ERR_PTR(height);
  750. depth = display_get_depth_of(dev, of_node);
  751. if (depth < 0)
  752. return ERR_PTR(depth);
  753. linebytes = display_get_linebytes_of(dev, of_node);
  754. if (linebytes < 0)
  755. return ERR_PTR(linebytes);
  756. format = display_get_validated_format(dev, depth, big_endian);
  757. if (IS_ERR(format))
  758. return ERR_CAST(format);
  759. if (!linebytes) {
  760. linebytes = drm_format_info_min_pitch(format, 0, width);
  761. if (drm_WARN_ON(dev, !linebytes))
  762. return ERR_PTR(-EINVAL);
  763. }
  764. fb_size = linebytes * height;
  765. /*
  766. * Try to figure out the address of the framebuffer. Unfortunately, Open
  767. * Firmware doesn't provide a standard way to do so. All we can do is a
  768. * dodgy heuristic that happens to work in practice.
  769. *
  770. * On most machines, the "address" property contains what we need, though
  771. * not on Matrox cards found in IBM machines. What appears to give good
  772. * results is to go through the PCI ranges and pick one that encloses the
  773. * "address" property. If none match, we pick the largest.
  774. */
  775. address = display_get_address_of(dev, of_node);
  776. if (address != OF_BAD_ADDR) {
  777. struct resource fb_res = DEFINE_RES_MEM(address, fb_size);
  778. res = ofdrm_find_fb_resource(odev, &fb_res);
  779. if (!res)
  780. return ERR_PTR(-EINVAL);
  781. if (resource_contains(res, &fb_res))
  782. fb_base = address;
  783. else
  784. fb_base = res->start;
  785. } else {
  786. struct resource fb_res = DEFINE_RES_MEM(0u, fb_size);
  787. res = ofdrm_find_fb_resource(odev, &fb_res);
  788. if (!res)
  789. return ERR_PTR(-EINVAL);
  790. fb_base = res->start;
  791. }
  792. /*
  793. * I/O resources
  794. */
  795. fb_pgbase = round_down(fb_base, PAGE_SIZE);
  796. fb_pgsize = fb_base - fb_pgbase + round_up(fb_size, PAGE_SIZE);
  797. ret = devm_aperture_acquire_for_platform_device(pdev, fb_pgbase, fb_pgsize);
  798. if (ret) {
  799. drm_err(dev, "could not acquire memory range %pr: error %d\n", &res, ret);
  800. return ERR_PTR(ret);
  801. }
  802. mem = devm_request_mem_region(&pdev->dev, fb_pgbase, fb_pgsize, drv->name);
  803. if (!mem) {
  804. drm_warn(dev, "could not acquire memory region %pr\n", &res);
  805. return ERR_PTR(-ENOMEM);
  806. }
  807. screen_base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
  808. if (!screen_base)
  809. return ERR_PTR(-ENOMEM);
  810. if (odev->funcs->cmap_ioremap) {
  811. void __iomem *cmap_base = odev->funcs->cmap_ioremap(odev, of_node, fb_base);
  812. if (IS_ERR(cmap_base)) {
  813. /* Don't fail; continue without colormap */
  814. drm_warn(dev, "could not find colormap: error %ld\n", PTR_ERR(cmap_base));
  815. } else {
  816. odev->cmap_base = cmap_base;
  817. }
  818. }
  819. /* EDID is optional */
  820. edid = display_get_edid_of(dev, of_node, odev->edid);
  821. /*
  822. * Firmware framebuffer
  823. */
  824. iosys_map_set_vaddr_iomem(&sysfb->fb_addr, screen_base);
  825. sysfb->fb_mode = drm_sysfb_mode(width, height, 0, 0);
  826. sysfb->fb_format = format;
  827. sysfb->fb_pitch = linebytes;
  828. if (odev->cmap_base)
  829. sysfb->fb_gamma_lut_size = OFDRM_GAMMA_LUT_SIZE;
  830. sysfb->edid = edid;
  831. drm_dbg(dev, "display mode={" DRM_MODE_FMT "}\n", DRM_MODE_ARG(&sysfb->fb_mode));
  832. drm_dbg(dev, "framebuffer format=%p4cc, size=%dx%d, linebytes=%d byte\n",
  833. &format->format, width, height, linebytes);
  834. /*
  835. * Mode-setting pipeline
  836. */
  837. ret = drmm_mode_config_init(dev);
  838. if (ret)
  839. return ERR_PTR(ret);
  840. max_width = max_t(unsigned long, width, DRM_SHADOW_PLANE_MAX_WIDTH);
  841. max_height = max_t(unsigned long, height, DRM_SHADOW_PLANE_MAX_HEIGHT);
  842. dev->mode_config.min_width = width;
  843. dev->mode_config.max_width = max_width;
  844. dev->mode_config.min_height = height;
  845. dev->mode_config.max_height = max_height;
  846. dev->mode_config.funcs = &ofdrm_mode_config_funcs;
  847. dev->mode_config.preferred_depth = format->depth;
  848. dev->mode_config.quirk_addfb_prefer_host_byte_order = true;
  849. /* Primary plane */
  850. nformats = drm_sysfb_build_fourcc_list(dev, &format->format, 1,
  851. odev->formats, ARRAY_SIZE(odev->formats));
  852. primary_plane = &odev->primary_plane;
  853. ret = drm_universal_plane_init(dev, primary_plane, 0, &ofdrm_primary_plane_funcs,
  854. odev->formats, nformats,
  855. ofdrm_primary_plane_format_modifiers,
  856. DRM_PLANE_TYPE_PRIMARY, NULL);
  857. if (ret)
  858. return ERR_PTR(ret);
  859. drm_plane_helper_add(primary_plane, &ofdrm_primary_plane_helper_funcs);
  860. drm_plane_enable_fb_damage_clips(primary_plane);
  861. /* CRTC */
  862. crtc = &odev->crtc;
  863. ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL,
  864. &ofdrm_crtc_funcs, NULL);
  865. if (ret)
  866. return ERR_PTR(ret);
  867. drm_crtc_helper_add(crtc, &ofdrm_crtc_helper_funcs);
  868. if (sysfb->fb_gamma_lut_size) {
  869. ret = drm_mode_crtc_set_gamma_size(crtc, sysfb->fb_gamma_lut_size);
  870. if (!ret)
  871. drm_crtc_enable_color_mgmt(crtc, 0, false, sysfb->fb_gamma_lut_size);
  872. }
  873. /* Encoder */
  874. encoder = &odev->encoder;
  875. ret = drm_encoder_init(dev, encoder, &ofdrm_encoder_funcs, DRM_MODE_ENCODER_NONE, NULL);
  876. if (ret)
  877. return ERR_PTR(ret);
  878. encoder->possible_crtcs = drm_crtc_mask(crtc);
  879. /* Connector */
  880. connector = &odev->connector;
  881. ret = drm_connector_init(dev, connector, &ofdrm_connector_funcs,
  882. DRM_MODE_CONNECTOR_Unknown);
  883. if (ret)
  884. return ERR_PTR(ret);
  885. drm_connector_helper_add(connector, &ofdrm_connector_helper_funcs);
  886. drm_connector_set_panel_orientation_with_quirk(connector,
  887. DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
  888. width, height);
  889. if (edid)
  890. drm_connector_attach_edid_property(connector);
  891. ret = drm_connector_attach_encoder(connector, encoder);
  892. if (ret)
  893. return ERR_PTR(ret);
  894. drm_mode_config_reset(dev);
  895. return odev;
  896. }
  897. /*
  898. * DRM driver
  899. */
  900. DEFINE_DRM_GEM_FOPS(ofdrm_fops);
  901. static struct drm_driver ofdrm_driver = {
  902. DRM_GEM_SHMEM_DRIVER_OPS,
  903. DRM_FBDEV_SHMEM_DRIVER_OPS,
  904. .name = DRIVER_NAME,
  905. .desc = DRIVER_DESC,
  906. .major = DRIVER_MAJOR,
  907. .minor = DRIVER_MINOR,
  908. .driver_features = DRIVER_ATOMIC | DRIVER_GEM | DRIVER_MODESET,
  909. .fops = &ofdrm_fops,
  910. };
  911. /*
  912. * Platform driver
  913. */
  914. static int ofdrm_probe(struct platform_device *pdev)
  915. {
  916. struct ofdrm_device *odev;
  917. struct drm_sysfb_device *sysfb;
  918. struct drm_device *dev;
  919. int ret;
  920. odev = ofdrm_device_create(&ofdrm_driver, pdev);
  921. if (IS_ERR(odev))
  922. return PTR_ERR(odev);
  923. sysfb = &odev->sysfb;
  924. dev = &sysfb->dev;
  925. ret = drm_dev_register(dev, 0);
  926. if (ret)
  927. return ret;
  928. drm_client_setup(dev, sysfb->fb_format);
  929. return 0;
  930. }
  931. static void ofdrm_remove(struct platform_device *pdev)
  932. {
  933. struct drm_device *dev = platform_get_drvdata(pdev);
  934. drm_dev_unplug(dev);
  935. }
  936. static const struct of_device_id ofdrm_of_match_display[] = {
  937. { .compatible = "display", },
  938. { },
  939. };
  940. MODULE_DEVICE_TABLE(of, ofdrm_of_match_display);
  941. static struct platform_driver ofdrm_platform_driver = {
  942. .driver = {
  943. .name = "of-display",
  944. .of_match_table = ofdrm_of_match_display,
  945. },
  946. .probe = ofdrm_probe,
  947. .remove = ofdrm_remove,
  948. };
  949. module_platform_driver(ofdrm_platform_driver);
  950. MODULE_DESCRIPTION(DRIVER_DESC);
  951. MODULE_LICENSE("GPL");