dmatest.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * DMA Engine test module
  4. *
  5. * Copyright (C) 2007 Atmel Corporation
  6. * Copyright (C) 2013 Intel Corporation
  7. */
  8. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  9. #include <linux/err.h>
  10. #include <linux/delay.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/dmaengine.h>
  13. #include <linux/freezer.h>
  14. #include <linux/init.h>
  15. #include <linux/kthread.h>
  16. #include <linux/sched/task.h>
  17. #include <linux/module.h>
  18. #include <linux/moduleparam.h>
  19. #include <linux/random.h>
  20. #include <linux/slab.h>
  21. #include <linux/wait.h>
  22. static bool nobounce;
  23. module_param(nobounce, bool, 0644);
  24. MODULE_PARM_DESC(nobounce, "Prevent using swiotlb buffer (default: use swiotlb buffer)");
  25. static unsigned int test_buf_size = 16384;
  26. module_param(test_buf_size, uint, 0644);
  27. MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
  28. static char test_device[32];
  29. module_param_string(device, test_device, sizeof(test_device), 0644);
  30. MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
  31. static unsigned int threads_per_chan = 1;
  32. module_param(threads_per_chan, uint, 0644);
  33. MODULE_PARM_DESC(threads_per_chan,
  34. "Number of threads to start per channel (default: 1)");
  35. static unsigned int max_channels;
  36. module_param(max_channels, uint, 0644);
  37. MODULE_PARM_DESC(max_channels,
  38. "Maximum number of channels to use (default: all)");
  39. static unsigned int iterations;
  40. module_param(iterations, uint, 0644);
  41. MODULE_PARM_DESC(iterations,
  42. "Iterations before stopping test (default: infinite)");
  43. static unsigned int dmatest;
  44. module_param(dmatest, uint, 0644);
  45. MODULE_PARM_DESC(dmatest,
  46. "dmatest 0-memcpy 1-memset (default: 0)");
  47. static unsigned int xor_sources = 3;
  48. module_param(xor_sources, uint, 0644);
  49. MODULE_PARM_DESC(xor_sources,
  50. "Number of xor source buffers (default: 3)");
  51. static unsigned int pq_sources = 3;
  52. module_param(pq_sources, uint, 0644);
  53. MODULE_PARM_DESC(pq_sources,
  54. "Number of p+q source buffers (default: 3)");
  55. static int timeout = 3000;
  56. module_param(timeout, int, 0644);
  57. MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
  58. "Pass -1 for infinite timeout");
  59. static bool noverify;
  60. module_param(noverify, bool, 0644);
  61. MODULE_PARM_DESC(noverify, "Disable data verification (default: verify)");
  62. static bool norandom;
  63. module_param(norandom, bool, 0644);
  64. MODULE_PARM_DESC(norandom, "Disable random offset setup (default: random)");
  65. static bool verbose;
  66. module_param(verbose, bool, 0644);
  67. MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)");
  68. static int alignment = -1;
  69. module_param(alignment, int, 0644);
  70. MODULE_PARM_DESC(alignment, "Custom data address alignment taken as 2^(alignment) (default: not used (-1))");
  71. static unsigned int transfer_size;
  72. module_param(transfer_size, uint, 0644);
  73. MODULE_PARM_DESC(transfer_size, "Optional custom transfer size in bytes (default: not used (0))");
  74. static bool polled;
  75. module_param(polled, bool, 0644);
  76. MODULE_PARM_DESC(polled, "Use polling for completion instead of interrupts");
  77. /**
  78. * struct dmatest_params - test parameters.
  79. * @nobounce: prevent using swiotlb buffer
  80. * @buf_size: size of the memcpy test buffer
  81. * @channel: bus ID of the channel to test
  82. * @device: bus ID of the DMA Engine to test
  83. * @threads_per_chan: number of threads to start per channel
  84. * @max_channels: maximum number of channels to use
  85. * @iterations: iterations before stopping test
  86. * @xor_sources: number of xor source buffers
  87. * @pq_sources: number of p+q source buffers
  88. * @timeout: transfer timeout in msec, -1 for infinite timeout
  89. * @noverify: disable data verification
  90. * @norandom: disable random offset setup
  91. * @alignment: custom data address alignment taken as 2^alignment
  92. * @transfer_size: custom transfer size in bytes
  93. * @polled: use polling for completion instead of interrupts
  94. */
  95. struct dmatest_params {
  96. bool nobounce;
  97. unsigned int buf_size;
  98. char channel[20];
  99. char device[32];
  100. unsigned int threads_per_chan;
  101. unsigned int max_channels;
  102. unsigned int iterations;
  103. unsigned int xor_sources;
  104. unsigned int pq_sources;
  105. int timeout;
  106. bool noverify;
  107. bool norandom;
  108. int alignment;
  109. unsigned int transfer_size;
  110. bool polled;
  111. };
  112. /**
  113. * struct dmatest_info - test information.
  114. * @params: test parameters
  115. * @channels: channels under test
  116. * @nr_channels: number of channels under test
  117. * @lock: access protection to the fields of this structure
  118. * @did_init: module has been initialized completely
  119. * @last_error: test has faced configuration issues
  120. */
  121. static struct dmatest_info {
  122. /* Test parameters */
  123. struct dmatest_params params;
  124. /* Internal state */
  125. struct list_head channels;
  126. unsigned int nr_channels;
  127. int last_error;
  128. struct mutex lock;
  129. bool did_init;
  130. } test_info = {
  131. .channels = LIST_HEAD_INIT(test_info.channels),
  132. .lock = __MUTEX_INITIALIZER(test_info.lock),
  133. };
  134. static int dmatest_run_set(const char *val, const struct kernel_param *kp);
  135. static int dmatest_run_get(char *val, const struct kernel_param *kp);
  136. static const struct kernel_param_ops run_ops = {
  137. .set = dmatest_run_set,
  138. .get = dmatest_run_get,
  139. };
  140. static bool dmatest_run;
  141. module_param_cb(run, &run_ops, &dmatest_run, 0644);
  142. MODULE_PARM_DESC(run, "Run the test (default: false)");
  143. static int dmatest_chan_set(const char *val, const struct kernel_param *kp);
  144. static int dmatest_chan_get(char *val, const struct kernel_param *kp);
  145. static const struct kernel_param_ops multi_chan_ops = {
  146. .set = dmatest_chan_set,
  147. .get = dmatest_chan_get,
  148. };
  149. static char test_channel[20];
  150. static struct kparam_string newchan_kps = {
  151. .string = test_channel,
  152. .maxlen = 20,
  153. };
  154. module_param_cb(channel, &multi_chan_ops, &newchan_kps, 0644);
  155. MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
  156. static int dmatest_test_list_get(char *val, const struct kernel_param *kp);
  157. static const struct kernel_param_ops test_list_ops = {
  158. .get = dmatest_test_list_get,
  159. };
  160. module_param_cb(test_list, &test_list_ops, NULL, 0444);
  161. MODULE_PARM_DESC(test_list, "Print current test list");
  162. /* Maximum amount of mismatched bytes in buffer to print */
  163. #define MAX_ERROR_COUNT 32
  164. /*
  165. * Initialization patterns. All bytes in the source buffer has bit 7
  166. * set, all bytes in the destination buffer has bit 7 cleared.
  167. *
  168. * Bit 6 is set for all bytes which are to be copied by the DMA
  169. * engine. Bit 5 is set for all bytes which are to be overwritten by
  170. * the DMA engine.
  171. *
  172. * The remaining bits are the inverse of a counter which increments by
  173. * one for each byte address.
  174. */
  175. #define PATTERN_SRC 0x80
  176. #define PATTERN_DST 0x00
  177. #define PATTERN_COPY 0x40
  178. #define PATTERN_OVERWRITE 0x20
  179. #define PATTERN_COUNT_MASK 0x1f
  180. #define PATTERN_MEMSET_IDX 0x01
  181. /* Fixed point arithmetic ops */
  182. #define FIXPT_SHIFT 8
  183. #define FIXPNT_MASK 0xFF
  184. #define FIXPT_TO_INT(a) ((a) >> FIXPT_SHIFT)
  185. #define INT_TO_FIXPT(a) ((a) << FIXPT_SHIFT)
  186. #define FIXPT_GET_FRAC(a) ((((a) & FIXPNT_MASK) * 100) >> FIXPT_SHIFT)
  187. /* poor man's completion - we want to use wait_event_freezable() on it */
  188. struct dmatest_done {
  189. bool done;
  190. wait_queue_head_t *wait;
  191. };
  192. struct dmatest_data {
  193. u8 **raw;
  194. u8 **aligned;
  195. gfp_t gfp_flags;
  196. unsigned int cnt;
  197. unsigned int off;
  198. };
  199. struct dmatest_thread {
  200. struct list_head node;
  201. struct dmatest_info *info;
  202. struct task_struct *task;
  203. struct dma_chan *chan;
  204. struct dmatest_data src;
  205. struct dmatest_data dst;
  206. enum dma_transaction_type type;
  207. wait_queue_head_t done_wait;
  208. struct dmatest_done test_done;
  209. bool done;
  210. bool pending;
  211. };
  212. struct dmatest_chan {
  213. struct list_head node;
  214. struct dma_chan *chan;
  215. struct list_head threads;
  216. };
  217. static DECLARE_WAIT_QUEUE_HEAD(thread_wait);
  218. static bool wait;
  219. static bool is_threaded_test_run(struct dmatest_info *info)
  220. {
  221. struct dmatest_chan *dtc;
  222. list_for_each_entry(dtc, &info->channels, node) {
  223. struct dmatest_thread *thread;
  224. list_for_each_entry(thread, &dtc->threads, node) {
  225. if (!thread->done && !thread->pending)
  226. return true;
  227. }
  228. }
  229. return false;
  230. }
  231. static bool is_threaded_test_pending(struct dmatest_info *info)
  232. {
  233. struct dmatest_chan *dtc;
  234. list_for_each_entry(dtc, &info->channels, node) {
  235. struct dmatest_thread *thread;
  236. list_for_each_entry(thread, &dtc->threads, node) {
  237. if (thread->pending)
  238. return true;
  239. }
  240. }
  241. return false;
  242. }
  243. static int dmatest_wait_get(char *val, const struct kernel_param *kp)
  244. {
  245. struct dmatest_info *info = &test_info;
  246. struct dmatest_params *params = &info->params;
  247. if (params->iterations)
  248. wait_event(thread_wait, !is_threaded_test_run(info));
  249. wait = true;
  250. return param_get_bool(val, kp);
  251. }
  252. static const struct kernel_param_ops wait_ops = {
  253. .get = dmatest_wait_get,
  254. .set = param_set_bool,
  255. };
  256. module_param_cb(wait, &wait_ops, &wait, 0444);
  257. MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)");
  258. static bool dmatest_match_channel(struct dmatest_params *params,
  259. struct dma_chan *chan)
  260. {
  261. if (params->channel[0] == '\0')
  262. return true;
  263. return strcmp(dma_chan_name(chan), params->channel) == 0;
  264. }
  265. static bool dmatest_match_device(struct dmatest_params *params,
  266. struct dma_device *device)
  267. {
  268. if (params->device[0] == '\0')
  269. return true;
  270. return strcmp(dev_name(device->dev), params->device) == 0;
  271. }
  272. static unsigned long dmatest_random(void)
  273. {
  274. unsigned long buf;
  275. get_random_bytes(&buf, sizeof(buf));
  276. return buf;
  277. }
  278. static inline u8 gen_inv_idx(u8 index, bool is_memset)
  279. {
  280. u8 val = is_memset ? PATTERN_MEMSET_IDX : index;
  281. return ~val & PATTERN_COUNT_MASK;
  282. }
  283. static inline u8 gen_src_value(u8 index, bool is_memset)
  284. {
  285. return PATTERN_SRC | gen_inv_idx(index, is_memset);
  286. }
  287. static inline u8 gen_dst_value(u8 index, bool is_memset)
  288. {
  289. return PATTERN_DST | gen_inv_idx(index, is_memset);
  290. }
  291. static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
  292. unsigned int buf_size, bool is_memset)
  293. {
  294. unsigned int i;
  295. u8 *buf;
  296. for (; (buf = *bufs); bufs++) {
  297. for (i = 0; i < start; i++)
  298. buf[i] = gen_src_value(i, is_memset);
  299. for ( ; i < start + len; i++)
  300. buf[i] = gen_src_value(i, is_memset) | PATTERN_COPY;
  301. for ( ; i < buf_size; i++)
  302. buf[i] = gen_src_value(i, is_memset);
  303. buf++;
  304. }
  305. }
  306. static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
  307. unsigned int buf_size, bool is_memset)
  308. {
  309. unsigned int i;
  310. u8 *buf;
  311. for (; (buf = *bufs); bufs++) {
  312. for (i = 0; i < start; i++)
  313. buf[i] = gen_dst_value(i, is_memset);
  314. for ( ; i < start + len; i++)
  315. buf[i] = gen_dst_value(i, is_memset) |
  316. PATTERN_OVERWRITE;
  317. for ( ; i < buf_size; i++)
  318. buf[i] = gen_dst_value(i, is_memset);
  319. }
  320. }
  321. static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
  322. unsigned int counter, bool is_srcbuf, bool is_memset)
  323. {
  324. u8 diff = actual ^ pattern;
  325. u8 expected = pattern | gen_inv_idx(counter, is_memset);
  326. const char *thread_name = current->comm;
  327. if (is_srcbuf)
  328. pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n",
  329. thread_name, index, expected, actual);
  330. else if ((pattern & PATTERN_COPY)
  331. && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
  332. pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n",
  333. thread_name, index, expected, actual);
  334. else if (diff & PATTERN_SRC)
  335. pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n",
  336. thread_name, index, expected, actual);
  337. else
  338. pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n",
  339. thread_name, index, expected, actual);
  340. }
  341. static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
  342. unsigned int end, unsigned int counter, u8 pattern,
  343. bool is_srcbuf, bool is_memset)
  344. {
  345. unsigned int i;
  346. unsigned int error_count = 0;
  347. u8 actual;
  348. u8 expected;
  349. u8 *buf;
  350. unsigned int counter_orig = counter;
  351. for (; (buf = *bufs); bufs++) {
  352. counter = counter_orig;
  353. for (i = start; i < end; i++) {
  354. actual = buf[i];
  355. expected = pattern | gen_inv_idx(counter, is_memset);
  356. if (actual != expected) {
  357. if (error_count < MAX_ERROR_COUNT)
  358. dmatest_mismatch(actual, pattern, i,
  359. counter, is_srcbuf,
  360. is_memset);
  361. error_count++;
  362. }
  363. counter++;
  364. }
  365. }
  366. if (error_count > MAX_ERROR_COUNT)
  367. pr_warn("%s: %u errors suppressed\n",
  368. current->comm, error_count - MAX_ERROR_COUNT);
  369. return error_count;
  370. }
  371. static void dmatest_callback(void *arg)
  372. {
  373. struct dmatest_done *done = arg;
  374. struct dmatest_thread *thread =
  375. container_of(done, struct dmatest_thread, test_done);
  376. if (!thread->done) {
  377. done->done = true;
  378. wake_up_all(done->wait);
  379. } else {
  380. /*
  381. * If thread->done, it means that this callback occurred
  382. * after the parent thread has cleaned up. This can
  383. * happen in the case that driver doesn't implement
  384. * the terminate_all() functionality and a dma operation
  385. * did not occur within the timeout period
  386. */
  387. WARN(1, "dmatest: Kernel memory may be corrupted!!\n");
  388. }
  389. }
  390. static unsigned int min_odd(unsigned int x, unsigned int y)
  391. {
  392. unsigned int val = min(x, y);
  393. return val % 2 ? val : val - 1;
  394. }
  395. static void result(const char *err, unsigned int n, unsigned int src_off,
  396. unsigned int dst_off, unsigned int len, unsigned long data)
  397. {
  398. if (IS_ERR_VALUE(data)) {
  399. pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%ld)\n",
  400. current->comm, n, err, src_off, dst_off, len, data);
  401. } else {
  402. pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
  403. current->comm, n, err, src_off, dst_off, len, data);
  404. }
  405. }
  406. static void dbg_result(const char *err, unsigned int n, unsigned int src_off,
  407. unsigned int dst_off, unsigned int len,
  408. unsigned long data)
  409. {
  410. pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
  411. current->comm, n, err, src_off, dst_off, len, data);
  412. }
  413. #define verbose_result(err, n, src_off, dst_off, len, data) ({ \
  414. if (verbose) \
  415. result(err, n, src_off, dst_off, len, data); \
  416. else \
  417. dbg_result(err, n, src_off, dst_off, len, data);\
  418. })
  419. static unsigned long long dmatest_persec(s64 runtime, unsigned int val)
  420. {
  421. unsigned long long per_sec = 1000000;
  422. if (runtime <= 0)
  423. return 0;
  424. /* drop precision until runtime is 32-bits */
  425. while (runtime > UINT_MAX) {
  426. runtime >>= 1;
  427. per_sec <<= 1;
  428. }
  429. per_sec *= val;
  430. per_sec = INT_TO_FIXPT(per_sec);
  431. do_div(per_sec, (u32)runtime);
  432. return per_sec;
  433. }
  434. static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len)
  435. {
  436. return FIXPT_TO_INT(dmatest_persec(runtime, len >> 10));
  437. }
  438. static void __dmatest_free_test_data(struct dmatest_data *d, unsigned int cnt)
  439. {
  440. unsigned int i;
  441. for (i = 0; i < cnt; i++)
  442. kfree(d->raw[i]);
  443. kfree(d->aligned);
  444. kfree(d->raw);
  445. }
  446. static void dmatest_free_test_data(struct dmatest_data *d)
  447. {
  448. __dmatest_free_test_data(d, d->cnt);
  449. }
  450. static int dmatest_alloc_test_data(struct dmatest_data *d,
  451. unsigned int buf_size, u8 align)
  452. {
  453. unsigned int i = 0;
  454. d->raw = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL);
  455. if (!d->raw)
  456. return -ENOMEM;
  457. d->aligned = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL);
  458. if (!d->aligned)
  459. goto err;
  460. for (i = 0; i < d->cnt; i++) {
  461. d->raw[i] = kmalloc(buf_size + align, d->gfp_flags);
  462. if (!d->raw[i])
  463. goto err;
  464. /* align to alignment restriction */
  465. if (align)
  466. d->aligned[i] = PTR_ALIGN(d->raw[i], align);
  467. else
  468. d->aligned[i] = d->raw[i];
  469. }
  470. return 0;
  471. err:
  472. __dmatest_free_test_data(d, i);
  473. return -ENOMEM;
  474. }
  475. /*
  476. * This function repeatedly tests DMA transfers of various lengths and
  477. * offsets for a given operation type until it is told to exit by
  478. * kthread_stop(). There may be multiple threads running this function
  479. * in parallel for a single channel, and there may be multiple channels
  480. * being tested in parallel.
  481. *
  482. * Before each test, the source and destination buffer is initialized
  483. * with a known pattern. This pattern is different depending on
  484. * whether it's in an area which is supposed to be copied or
  485. * overwritten, and different in the source and destination buffers.
  486. * So if the DMA engine doesn't copy exactly what we tell it to copy,
  487. * we'll notice.
  488. */
  489. static int dmatest_func(void *data)
  490. {
  491. struct dmatest_thread *thread = data;
  492. struct dmatest_done *done = &thread->test_done;
  493. struct dmatest_info *info;
  494. struct dmatest_params *params;
  495. struct dma_chan *chan;
  496. struct dma_device *dev;
  497. struct device *dma_dev;
  498. unsigned int error_count;
  499. unsigned int failed_tests = 0;
  500. unsigned int total_tests = 0;
  501. dma_cookie_t cookie;
  502. enum dma_status status;
  503. enum dma_ctrl_flags flags;
  504. u8 *pq_coefs = NULL;
  505. int ret;
  506. unsigned int buf_size;
  507. struct dmatest_data *src;
  508. struct dmatest_data *dst;
  509. int i;
  510. ktime_t ktime, start, diff;
  511. ktime_t filltime = 0;
  512. ktime_t comparetime = 0;
  513. s64 runtime = 0;
  514. unsigned long long total_len = 0;
  515. unsigned long long iops = 0;
  516. u8 align = 0;
  517. bool is_memset = false;
  518. dma_addr_t *srcs;
  519. dma_addr_t *dma_pq;
  520. set_freezable();
  521. ret = -ENOMEM;
  522. smp_rmb();
  523. thread->pending = false;
  524. info = thread->info;
  525. params = &info->params;
  526. chan = thread->chan;
  527. dev = chan->device;
  528. dma_dev = dmaengine_get_dma_device(chan);
  529. src = &thread->src;
  530. dst = &thread->dst;
  531. if (thread->type == DMA_MEMCPY) {
  532. align = params->alignment < 0 ? dev->copy_align :
  533. params->alignment;
  534. src->cnt = dst->cnt = 1;
  535. } else if (thread->type == DMA_MEMSET) {
  536. align = params->alignment < 0 ? dev->fill_align :
  537. params->alignment;
  538. src->cnt = dst->cnt = 1;
  539. is_memset = true;
  540. } else if (thread->type == DMA_XOR) {
  541. /* force odd to ensure dst = src */
  542. src->cnt = min_odd(params->xor_sources | 1, dev->max_xor);
  543. dst->cnt = 1;
  544. align = params->alignment < 0 ? dev->xor_align :
  545. params->alignment;
  546. } else if (thread->type == DMA_PQ) {
  547. /* force odd to ensure dst = src */
  548. src->cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0));
  549. dst->cnt = 2;
  550. align = params->alignment < 0 ? dev->pq_align :
  551. params->alignment;
  552. pq_coefs = kmalloc(params->pq_sources + 1, GFP_KERNEL);
  553. if (!pq_coefs)
  554. goto err_thread_type;
  555. for (i = 0; i < src->cnt; i++)
  556. pq_coefs[i] = 1;
  557. } else
  558. goto err_thread_type;
  559. /* Check if buffer count fits into map count variable (u8) */
  560. if ((src->cnt + dst->cnt) >= 255) {
  561. pr_err("too many buffers (%d of 255 supported)\n",
  562. src->cnt + dst->cnt);
  563. goto err_free_coefs;
  564. }
  565. buf_size = params->buf_size;
  566. if (1 << align > buf_size) {
  567. pr_err("%u-byte buffer too small for %d-byte alignment\n",
  568. buf_size, 1 << align);
  569. goto err_free_coefs;
  570. }
  571. src->gfp_flags = GFP_KERNEL;
  572. dst->gfp_flags = GFP_KERNEL;
  573. if (params->nobounce) {
  574. src->gfp_flags = GFP_DMA;
  575. dst->gfp_flags = GFP_DMA;
  576. }
  577. if (dmatest_alloc_test_data(src, buf_size, align) < 0)
  578. goto err_free_coefs;
  579. if (dmatest_alloc_test_data(dst, buf_size, align) < 0)
  580. goto err_src;
  581. set_user_nice(current, 10);
  582. srcs = kzalloc_objs(dma_addr_t, src->cnt);
  583. if (!srcs)
  584. goto err_dst;
  585. dma_pq = kzalloc_objs(dma_addr_t, dst->cnt);
  586. if (!dma_pq)
  587. goto err_srcs_array;
  588. /*
  589. * src and dst buffers are freed by ourselves below
  590. */
  591. if (params->polled)
  592. flags = DMA_CTRL_ACK;
  593. else
  594. flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
  595. ktime = ktime_get();
  596. while (!(kthread_should_stop() ||
  597. (params->iterations && total_tests >= params->iterations))) {
  598. struct dma_async_tx_descriptor *tx = NULL;
  599. struct dmaengine_unmap_data *um;
  600. dma_addr_t *dsts;
  601. unsigned int len;
  602. total_tests++;
  603. if (params->transfer_size) {
  604. if (params->transfer_size >= buf_size) {
  605. pr_err("%u-byte transfer size must be lower than %u-buffer size\n",
  606. params->transfer_size, buf_size);
  607. break;
  608. }
  609. len = params->transfer_size;
  610. } else if (params->norandom) {
  611. len = buf_size;
  612. } else {
  613. len = dmatest_random() % buf_size + 1;
  614. }
  615. /* Do not alter transfer size explicitly defined by user */
  616. if (!params->transfer_size) {
  617. len = (len >> align) << align;
  618. if (!len)
  619. len = 1 << align;
  620. }
  621. total_len += len;
  622. if (params->norandom) {
  623. src->off = 0;
  624. dst->off = 0;
  625. } else {
  626. src->off = dmatest_random() % (buf_size - len + 1);
  627. dst->off = dmatest_random() % (buf_size - len + 1);
  628. src->off = (src->off >> align) << align;
  629. dst->off = (dst->off >> align) << align;
  630. }
  631. if (!params->noverify) {
  632. start = ktime_get();
  633. dmatest_init_srcs(src->aligned, src->off, len,
  634. buf_size, is_memset);
  635. dmatest_init_dsts(dst->aligned, dst->off, len,
  636. buf_size, is_memset);
  637. diff = ktime_sub(ktime_get(), start);
  638. filltime = ktime_add(filltime, diff);
  639. }
  640. um = dmaengine_get_unmap_data(dma_dev, src->cnt + dst->cnt,
  641. GFP_KERNEL);
  642. if (!um) {
  643. failed_tests++;
  644. result("unmap data NULL", total_tests,
  645. src->off, dst->off, len, ret);
  646. continue;
  647. }
  648. um->len = buf_size;
  649. for (i = 0; i < src->cnt; i++) {
  650. void *buf = src->aligned[i];
  651. struct page *pg = virt_to_page(buf);
  652. unsigned long pg_off = offset_in_page(buf);
  653. um->addr[i] = dma_map_page(dma_dev, pg, pg_off,
  654. um->len, DMA_TO_DEVICE);
  655. srcs[i] = um->addr[i] + src->off;
  656. ret = dma_mapping_error(dma_dev, um->addr[i]);
  657. if (ret) {
  658. result("src mapping error", total_tests,
  659. src->off, dst->off, len, ret);
  660. goto error_unmap_continue;
  661. }
  662. um->to_cnt++;
  663. }
  664. /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
  665. dsts = &um->addr[src->cnt];
  666. for (i = 0; i < dst->cnt; i++) {
  667. void *buf = dst->aligned[i];
  668. struct page *pg = virt_to_page(buf);
  669. unsigned long pg_off = offset_in_page(buf);
  670. dsts[i] = dma_map_page(dma_dev, pg, pg_off, um->len,
  671. DMA_BIDIRECTIONAL);
  672. ret = dma_mapping_error(dma_dev, dsts[i]);
  673. if (ret) {
  674. result("dst mapping error", total_tests,
  675. src->off, dst->off, len, ret);
  676. goto error_unmap_continue;
  677. }
  678. um->bidi_cnt++;
  679. }
  680. if (thread->type == DMA_MEMCPY)
  681. tx = dev->device_prep_dma_memcpy(chan,
  682. dsts[0] + dst->off,
  683. srcs[0], len, flags);
  684. else if (thread->type == DMA_MEMSET)
  685. tx = dev->device_prep_dma_memset(chan,
  686. dsts[0] + dst->off,
  687. *(src->aligned[0] + src->off),
  688. len, flags);
  689. else if (thread->type == DMA_XOR)
  690. tx = dev->device_prep_dma_xor(chan,
  691. dsts[0] + dst->off,
  692. srcs, src->cnt,
  693. len, flags);
  694. else if (thread->type == DMA_PQ) {
  695. for (i = 0; i < dst->cnt; i++)
  696. dma_pq[i] = dsts[i] + dst->off;
  697. tx = dev->device_prep_dma_pq(chan, dma_pq, srcs,
  698. src->cnt, pq_coefs,
  699. len, flags);
  700. }
  701. if (!tx) {
  702. result("prep error", total_tests, src->off,
  703. dst->off, len, ret);
  704. msleep(100);
  705. goto error_unmap_continue;
  706. }
  707. done->done = false;
  708. if (!params->polled) {
  709. tx->callback = dmatest_callback;
  710. tx->callback_param = done;
  711. }
  712. cookie = tx->tx_submit(tx);
  713. if (dma_submit_error(cookie)) {
  714. result("submit error", total_tests, src->off,
  715. dst->off, len, ret);
  716. msleep(100);
  717. goto error_unmap_continue;
  718. }
  719. if (params->polled) {
  720. status = dma_sync_wait(chan, cookie);
  721. dmaengine_terminate_sync(chan);
  722. if (status == DMA_COMPLETE)
  723. done->done = true;
  724. } else {
  725. dma_async_issue_pending(chan);
  726. wait_event_freezable_timeout(thread->done_wait,
  727. done->done,
  728. msecs_to_jiffies(params->timeout));
  729. status = dma_async_is_tx_complete(chan, cookie, NULL,
  730. NULL);
  731. }
  732. if (!done->done) {
  733. result("test timed out", total_tests, src->off, dst->off,
  734. len, 0);
  735. goto error_unmap_continue;
  736. } else if (status != DMA_COMPLETE &&
  737. !(dma_has_cap(DMA_COMPLETION_NO_ORDER,
  738. dev->cap_mask) &&
  739. status == DMA_OUT_OF_ORDER)) {
  740. result(status == DMA_ERROR ?
  741. "completion error status" :
  742. "completion busy status", total_tests, src->off,
  743. dst->off, len, ret);
  744. goto error_unmap_continue;
  745. }
  746. dmaengine_unmap_put(um);
  747. if (params->noverify) {
  748. verbose_result("test passed", total_tests, src->off,
  749. dst->off, len, 0);
  750. continue;
  751. }
  752. start = ktime_get();
  753. pr_debug("%s: verifying source buffer...\n", current->comm);
  754. error_count = dmatest_verify(src->aligned, 0, src->off,
  755. 0, PATTERN_SRC, true, is_memset);
  756. error_count += dmatest_verify(src->aligned, src->off,
  757. src->off + len, src->off,
  758. PATTERN_SRC | PATTERN_COPY, true, is_memset);
  759. error_count += dmatest_verify(src->aligned, src->off + len,
  760. buf_size, src->off + len,
  761. PATTERN_SRC, true, is_memset);
  762. pr_debug("%s: verifying dest buffer...\n", current->comm);
  763. error_count += dmatest_verify(dst->aligned, 0, dst->off,
  764. 0, PATTERN_DST, false, is_memset);
  765. error_count += dmatest_verify(dst->aligned, dst->off,
  766. dst->off + len, src->off,
  767. PATTERN_SRC | PATTERN_COPY, false, is_memset);
  768. error_count += dmatest_verify(dst->aligned, dst->off + len,
  769. buf_size, dst->off + len,
  770. PATTERN_DST, false, is_memset);
  771. diff = ktime_sub(ktime_get(), start);
  772. comparetime = ktime_add(comparetime, diff);
  773. if (error_count) {
  774. result("data error", total_tests, src->off, dst->off,
  775. len, error_count);
  776. failed_tests++;
  777. } else {
  778. verbose_result("test passed", total_tests, src->off,
  779. dst->off, len, 0);
  780. }
  781. continue;
  782. error_unmap_continue:
  783. dmaengine_unmap_put(um);
  784. failed_tests++;
  785. }
  786. ktime = ktime_sub(ktime_get(), ktime);
  787. ktime = ktime_sub(ktime, comparetime);
  788. ktime = ktime_sub(ktime, filltime);
  789. runtime = ktime_to_us(ktime);
  790. ret = 0;
  791. kfree(dma_pq);
  792. err_srcs_array:
  793. kfree(srcs);
  794. err_dst:
  795. dmatest_free_test_data(dst);
  796. err_src:
  797. dmatest_free_test_data(src);
  798. err_free_coefs:
  799. kfree(pq_coefs);
  800. err_thread_type:
  801. iops = dmatest_persec(runtime, total_tests);
  802. pr_info("%s: summary %u tests, %u failures %llu.%02llu iops %llu KB/s (%d)\n",
  803. current->comm, total_tests, failed_tests,
  804. FIXPT_TO_INT(iops), FIXPT_GET_FRAC(iops),
  805. dmatest_KBs(runtime, total_len), ret);
  806. /* terminate all transfers on specified channels */
  807. if (ret || failed_tests)
  808. dmaengine_terminate_sync(chan);
  809. thread->done = true;
  810. wake_up(&thread_wait);
  811. return ret;
  812. }
  813. static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
  814. {
  815. struct dmatest_thread *thread;
  816. struct dmatest_thread *_thread;
  817. int ret;
  818. list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
  819. ret = kthread_stop(thread->task);
  820. pr_debug("thread %s exited with status %d\n",
  821. thread->task->comm, ret);
  822. list_del(&thread->node);
  823. put_task_struct(thread->task);
  824. kfree(thread);
  825. }
  826. /* terminate all transfers on specified channels */
  827. dmaengine_terminate_sync(dtc->chan);
  828. kfree(dtc);
  829. }
  830. static int dmatest_add_threads(struct dmatest_info *info,
  831. struct dmatest_chan *dtc, enum dma_transaction_type type)
  832. {
  833. struct dmatest_params *params = &info->params;
  834. struct dmatest_thread *thread;
  835. struct dma_chan *chan = dtc->chan;
  836. char *op;
  837. unsigned int i;
  838. if (type == DMA_MEMCPY)
  839. op = "copy";
  840. else if (type == DMA_MEMSET)
  841. op = "set";
  842. else if (type == DMA_XOR)
  843. op = "xor";
  844. else if (type == DMA_PQ)
  845. op = "pq";
  846. else
  847. return -EINVAL;
  848. for (i = 0; i < params->threads_per_chan; i++) {
  849. thread = kzalloc_obj(struct dmatest_thread);
  850. if (!thread) {
  851. pr_warn("No memory for %s-%s%u\n",
  852. dma_chan_name(chan), op, i);
  853. break;
  854. }
  855. thread->info = info;
  856. thread->chan = dtc->chan;
  857. thread->type = type;
  858. thread->test_done.wait = &thread->done_wait;
  859. init_waitqueue_head(&thread->done_wait);
  860. smp_wmb();
  861. thread->task = kthread_create(dmatest_func, thread, "%s-%s%u",
  862. dma_chan_name(chan), op, i);
  863. if (IS_ERR(thread->task)) {
  864. pr_warn("Failed to create thread %s-%s%u\n",
  865. dma_chan_name(chan), op, i);
  866. kfree(thread);
  867. break;
  868. }
  869. /* srcbuf and dstbuf are allocated by the thread itself */
  870. get_task_struct(thread->task);
  871. list_add_tail(&thread->node, &dtc->threads);
  872. thread->pending = true;
  873. }
  874. return i;
  875. }
  876. static int dmatest_add_channel(struct dmatest_info *info,
  877. struct dma_chan *chan)
  878. {
  879. struct dmatest_chan *dtc;
  880. struct dma_device *dma_dev = chan->device;
  881. unsigned int thread_count = 0;
  882. int cnt;
  883. dtc = kmalloc_obj(struct dmatest_chan);
  884. if (!dtc) {
  885. pr_warn("No memory for %s\n", dma_chan_name(chan));
  886. return -ENOMEM;
  887. }
  888. dtc->chan = chan;
  889. INIT_LIST_HEAD(&dtc->threads);
  890. if (dma_has_cap(DMA_COMPLETION_NO_ORDER, dma_dev->cap_mask) &&
  891. info->params.polled) {
  892. info->params.polled = false;
  893. pr_warn("DMA_COMPLETION_NO_ORDER, polled disabled\n");
  894. }
  895. if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
  896. if (dmatest == 0) {
  897. cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
  898. thread_count += cnt > 0 ? cnt : 0;
  899. }
  900. }
  901. if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
  902. if (dmatest == 1) {
  903. cnt = dmatest_add_threads(info, dtc, DMA_MEMSET);
  904. thread_count += cnt > 0 ? cnt : 0;
  905. }
  906. }
  907. if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
  908. cnt = dmatest_add_threads(info, dtc, DMA_XOR);
  909. thread_count += cnt > 0 ? cnt : 0;
  910. }
  911. if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
  912. cnt = dmatest_add_threads(info, dtc, DMA_PQ);
  913. thread_count += cnt > 0 ? cnt : 0;
  914. }
  915. pr_info("Added %u threads using %s\n",
  916. thread_count, dma_chan_name(chan));
  917. list_add_tail(&dtc->node, &info->channels);
  918. info->nr_channels++;
  919. return 0;
  920. }
  921. static bool filter(struct dma_chan *chan, void *param)
  922. {
  923. return dmatest_match_channel(param, chan) && dmatest_match_device(param, chan->device);
  924. }
  925. static void request_channels(struct dmatest_info *info,
  926. enum dma_transaction_type type)
  927. {
  928. dma_cap_mask_t mask;
  929. dma_cap_zero(mask);
  930. dma_cap_set(type, mask);
  931. for (;;) {
  932. struct dmatest_params *params = &info->params;
  933. struct dma_chan *chan;
  934. chan = dma_request_channel(mask, filter, params);
  935. if (chan) {
  936. if (dmatest_add_channel(info, chan)) {
  937. dma_release_channel(chan);
  938. break; /* add_channel failed, punt */
  939. }
  940. } else
  941. break; /* no more channels available */
  942. if (params->max_channels &&
  943. info->nr_channels >= params->max_channels)
  944. break; /* we have all we need */
  945. }
  946. }
  947. static void add_threaded_test(struct dmatest_info *info)
  948. {
  949. struct dmatest_params *params = &info->params;
  950. /* Copy test parameters */
  951. params->nobounce = nobounce;
  952. params->buf_size = test_buf_size;
  953. strscpy(params->channel, strim(test_channel), sizeof(params->channel));
  954. strscpy(params->device, strim(test_device), sizeof(params->device));
  955. params->threads_per_chan = threads_per_chan;
  956. params->max_channels = max_channels;
  957. params->iterations = iterations;
  958. params->xor_sources = xor_sources;
  959. params->pq_sources = pq_sources;
  960. params->timeout = timeout;
  961. params->noverify = noverify;
  962. params->norandom = norandom;
  963. params->alignment = alignment;
  964. params->transfer_size = transfer_size;
  965. params->polled = polled;
  966. request_channels(info, DMA_MEMCPY);
  967. request_channels(info, DMA_MEMSET);
  968. request_channels(info, DMA_XOR);
  969. request_channels(info, DMA_PQ);
  970. }
  971. static void run_pending_tests(struct dmatest_info *info)
  972. {
  973. struct dmatest_chan *dtc;
  974. unsigned int thread_count = 0;
  975. list_for_each_entry(dtc, &info->channels, node) {
  976. struct dmatest_thread *thread;
  977. thread_count = 0;
  978. list_for_each_entry(thread, &dtc->threads, node) {
  979. wake_up_process(thread->task);
  980. thread_count++;
  981. }
  982. pr_info("Started %u threads using %s\n",
  983. thread_count, dma_chan_name(dtc->chan));
  984. }
  985. }
  986. static void stop_threaded_test(struct dmatest_info *info)
  987. {
  988. struct dmatest_chan *dtc, *_dtc;
  989. struct dma_chan *chan;
  990. list_for_each_entry_safe(dtc, _dtc, &info->channels, node) {
  991. list_del(&dtc->node);
  992. chan = dtc->chan;
  993. dmatest_cleanup_channel(dtc);
  994. pr_debug("dropped channel %s\n", dma_chan_name(chan));
  995. dma_release_channel(chan);
  996. }
  997. info->nr_channels = 0;
  998. }
  999. static void start_threaded_tests(struct dmatest_info *info)
  1000. {
  1001. /* we might be called early to set run=, defer running until all
  1002. * parameters have been evaluated
  1003. */
  1004. if (!info->did_init)
  1005. return;
  1006. run_pending_tests(info);
  1007. }
  1008. static int dmatest_run_get(char *val, const struct kernel_param *kp)
  1009. {
  1010. struct dmatest_info *info = &test_info;
  1011. mutex_lock(&info->lock);
  1012. if (is_threaded_test_run(info)) {
  1013. dmatest_run = true;
  1014. } else {
  1015. if (!is_threaded_test_pending(info))
  1016. stop_threaded_test(info);
  1017. dmatest_run = false;
  1018. }
  1019. mutex_unlock(&info->lock);
  1020. return param_get_bool(val, kp);
  1021. }
  1022. static int dmatest_run_set(const char *val, const struct kernel_param *kp)
  1023. {
  1024. struct dmatest_info *info = &test_info;
  1025. int ret;
  1026. mutex_lock(&info->lock);
  1027. ret = param_set_bool(val, kp);
  1028. if (ret) {
  1029. mutex_unlock(&info->lock);
  1030. return ret;
  1031. } else if (dmatest_run) {
  1032. if (!is_threaded_test_pending(info)) {
  1033. /*
  1034. * We have nothing to run. This can be due to:
  1035. */
  1036. ret = info->last_error;
  1037. if (ret) {
  1038. /* 1) Misconfiguration */
  1039. pr_err("Channel misconfigured, can't continue\n");
  1040. mutex_unlock(&info->lock);
  1041. return ret;
  1042. } else {
  1043. /* 2) We rely on defaults */
  1044. pr_info("No channels configured, continue with any\n");
  1045. if (!is_threaded_test_run(info))
  1046. stop_threaded_test(info);
  1047. add_threaded_test(info);
  1048. }
  1049. }
  1050. start_threaded_tests(info);
  1051. } else {
  1052. stop_threaded_test(info);
  1053. }
  1054. mutex_unlock(&info->lock);
  1055. return ret;
  1056. }
  1057. static int dmatest_chan_set(const char *val, const struct kernel_param *kp)
  1058. {
  1059. struct dmatest_info *info = &test_info;
  1060. struct dmatest_chan *dtc;
  1061. char chan_reset_val[20];
  1062. int ret;
  1063. mutex_lock(&info->lock);
  1064. ret = param_set_copystring(val, kp);
  1065. if (ret) {
  1066. mutex_unlock(&info->lock);
  1067. return ret;
  1068. }
  1069. /*Clear any previously run threads */
  1070. if (!is_threaded_test_run(info) && !is_threaded_test_pending(info))
  1071. stop_threaded_test(info);
  1072. /* Reject channels that are already registered */
  1073. if (is_threaded_test_pending(info)) {
  1074. list_for_each_entry(dtc, &info->channels, node) {
  1075. if (strcmp(dma_chan_name(dtc->chan),
  1076. strim(test_channel)) == 0) {
  1077. dtc = list_last_entry(&info->channels,
  1078. struct dmatest_chan,
  1079. node);
  1080. strscpy(chan_reset_val,
  1081. dma_chan_name(dtc->chan),
  1082. sizeof(chan_reset_val));
  1083. ret = -EBUSY;
  1084. goto add_chan_err;
  1085. }
  1086. }
  1087. }
  1088. add_threaded_test(info);
  1089. /* Check if channel was added successfully */
  1090. if (!list_empty(&info->channels)) {
  1091. /*
  1092. * if new channel was not successfully added, revert the
  1093. * "test_channel" string to the name of the last successfully
  1094. * added channel. exception for when users issues empty string
  1095. * to channel parameter.
  1096. */
  1097. dtc = list_last_entry(&info->channels, struct dmatest_chan, node);
  1098. if ((strcmp(dma_chan_name(dtc->chan), strim(test_channel)) != 0)
  1099. && (strcmp("", strim(test_channel)) != 0)) {
  1100. ret = -EINVAL;
  1101. strscpy(chan_reset_val, dma_chan_name(dtc->chan),
  1102. sizeof(chan_reset_val));
  1103. goto add_chan_err;
  1104. }
  1105. } else {
  1106. /* Clear test_channel if no channels were added successfully */
  1107. strscpy(chan_reset_val, "", sizeof(chan_reset_val));
  1108. ret = -EBUSY;
  1109. goto add_chan_err;
  1110. }
  1111. info->last_error = ret;
  1112. mutex_unlock(&info->lock);
  1113. return ret;
  1114. add_chan_err:
  1115. param_set_copystring(chan_reset_val, kp);
  1116. info->last_error = ret;
  1117. mutex_unlock(&info->lock);
  1118. return ret;
  1119. }
  1120. static int dmatest_chan_get(char *val, const struct kernel_param *kp)
  1121. {
  1122. struct dmatest_info *info = &test_info;
  1123. mutex_lock(&info->lock);
  1124. if (!is_threaded_test_run(info) && !is_threaded_test_pending(info)) {
  1125. stop_threaded_test(info);
  1126. strscpy(test_channel, "", sizeof(test_channel));
  1127. }
  1128. mutex_unlock(&info->lock);
  1129. return param_get_string(val, kp);
  1130. }
  1131. static int dmatest_test_list_get(char *val, const struct kernel_param *kp)
  1132. {
  1133. struct dmatest_info *info = &test_info;
  1134. struct dmatest_chan *dtc;
  1135. unsigned int thread_count = 0;
  1136. list_for_each_entry(dtc, &info->channels, node) {
  1137. struct dmatest_thread *thread;
  1138. thread_count = 0;
  1139. list_for_each_entry(thread, &dtc->threads, node) {
  1140. thread_count++;
  1141. }
  1142. pr_info("%u threads using %s\n",
  1143. thread_count, dma_chan_name(dtc->chan));
  1144. }
  1145. return 0;
  1146. }
  1147. static int __init dmatest_init(void)
  1148. {
  1149. struct dmatest_info *info = &test_info;
  1150. struct dmatest_params *params = &info->params;
  1151. if (dmatest_run) {
  1152. mutex_lock(&info->lock);
  1153. add_threaded_test(info);
  1154. run_pending_tests(info);
  1155. mutex_unlock(&info->lock);
  1156. }
  1157. if (params->iterations && wait)
  1158. wait_event(thread_wait, !is_threaded_test_run(info));
  1159. /* module parameters are stable, inittime tests are started,
  1160. * let userspace take over 'run' control
  1161. */
  1162. info->did_init = true;
  1163. return 0;
  1164. }
  1165. /* when compiled-in wait for drivers to load first */
  1166. late_initcall(dmatest_init);
  1167. static void __exit dmatest_exit(void)
  1168. {
  1169. struct dmatest_info *info = &test_info;
  1170. mutex_lock(&info->lock);
  1171. stop_threaded_test(info);
  1172. mutex_unlock(&info->lock);
  1173. }
  1174. module_exit(dmatest_exit);
  1175. MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
  1176. MODULE_DESCRIPTION("DMA Engine test module");
  1177. MODULE_LICENSE("GPL v2");